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freiberufler SV-UVM VERIFICATION ENGINEER auf freelance.de

SV-UVM VERIFICATION ENGINEER

offline
  • 50€/Stunde
  • 85716 Unterschleißheim
  • Europa
  • bn
  • 09.08.2018
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Kurzvorstellung

I have a proven track record of consistent performance with excellence in my previous organizations and achieved many successes throughout my professional career of 7.9+ years, including design, verification, development, debugging etc.

Auszug Referenzen (1)

"YES,"
LEAD VERIFICATION ENGINEER
SAIKAT SANA
Tätigkeitszeitraum

5/2017 – 6/2018

Tätigkeitsbeschreibung

 Leading the team of JB4 and also responsible for developing the environment & coding testcases for various features of JB4 using SV & UVM.
 Executed regressions & responsible for Code and Functional Coverage Closures.
 Created assertion based checker for HCEn to FCEn mapping and AC timing parameter for Host side.
 Helping in NOC verification by porting tests and debugging.

Eingesetzte Qualifikationen

Digitaltechnik / Digitalelektronik

Qualifikationen

  • Lead verification engineer
  • Technische Beratung

Projekt‐ & Berufserfahrung

LEAD VERIFICATION ENGINEER
SANDISK(WDC), Bangalore
5/2017 – 6/2018 (1 Jahr, 2 Monate)
High-Tech- und Elektroindustrie
Tätigkeitszeitraum

5/2017 – 6/2018

Tätigkeitsbeschreibung

 Leading the team of JB4 and also responsible for developing the environment & coding testcases for various features of JB4 using SV & UVM.
 Executed regressions & responsible for Code and Functional Coverage Closures.
 Created assertion based checker for HCEn to FCEn mapping and AC timing parameter for Host side.
 Helping in NOC verification by porting tests and debugging.

Eingesetzte Qualifikationen

Digitaltechnik / Digitalelektronik

Ausbildung

UVM
Ausbildung
2011
BANGALORE
SYSTEM VERILOG
Ausbildung
2011
BANGALORE

Weitere Kenntnisse

I have done my Bachelor of Technology in Electrical Engineering in the year 2010 with 72.4% marks. 7.9 Years of ASIC Verification experience in various phases of Development and Maintenance. Through project participation all along I possess enough analytical skills to solve complex, cross-functional and technical issues. Expertise in various languages (Verilog, System Verilog), Methodologies (UVM, OVM) and various protocols (USB 2.0, Ethernet, Flash Interface, Interlaken etc.). I am looking for a challenging career in VLSI Verification Domain, where I can prove myself worthy and get a chance to further develop myself as a professional.

Persönliche Daten

Sprache
  • Bengalisch (Muttersprache)
Reisebereitschaft
Europa
Arbeitserlaubnis
  • Europäische Union
Profilaufrufe
728
Alter
35
Berufserfahrung
13 Jahre und 6 Monate (seit 10/2010)

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