Senior FPGA & Embedded Eng.
- Verfügbarkeit einsehen
- 0 Referenzen
- 70€/Stunde
- 22457 Hamburg
- Europa
- he | en | de
- 03.10.2019
Kurzvorstellung
Qualifikationen
Projekt‐ & Berufserfahrung
1/2019 – 8/2019
Tätigkeitsbeschreibung
• A part-remote-part-onsite project of a high speed imaging system.
• development of a high speed imaging system receiving image information from 12 sources in parallel, and sending it to the host via 10g-KR Ethernet optical link
• Incorporating a micro-controller system in the FPGA for configuration and control, communicating with the host over 1g Ethernet 1000BASE-T link
• Development of the microcontroller's bare-metal c code
• development of a fully-automatic TCL based scripting environment for the FPGA synthesis and implementation
• Lab testing and cooperation with the SW and HW team
Embedded Entwicklung / hardwarenahe Entwicklung, Embedded Linux, Field Programmable Gate Array (FPGA), Vivado (Xilinx), Python, TCL/TK
1/2018 – 1/2019
Tätigkeitsbeschreibung
• A remote project implementing a complete wifi 802.11agn PHY in an FPGA
• Implementing the 802.11agn PHY TX & RX layer (qualization, frquency offset correction, de-/encoding, de/modulatoin, packet detection etc.)
• The packets are sent/received to/from the host via FX3-USB3 device over VITA protocol
• To allow for smooth communication, a part of the MAC layer was also implemented, so ACK messages could be automatically generated and transmitted whenever necessary in the time frames described by the standard
• Reduced project costs by successfully implementing dual channels on a low-cost Xilinx Spartan-6 FPGA
• development of a fully-automatic TCL based scripting environment for the FPGA synthesis and implementation
• Lab testing and support in integration and SW driver development on the host
Embedded Entwicklung / hardwarenahe Entwicklung, Embedded Linux, Field Programmable Gate Array (FPGA), Vivado (Xilinx), Python, TCL/TK
8/2015 – offen
Tätigkeitsbeschreibung
• Developing an innovative system for the control of Particle-Accelerator-Magnets, incorporating 10 dynamic-reconfigurable areas on a single Zynq FPGA
• Performing the complete design, verification and implementation of the new generation of Particle-Detectors using a Zynq7000 FPGA. The Detectors receive data at a rate of over 30Gbps, and send it to the host over 10G Ethernet
• Creating and maintaining the FPGA build-flow-automation scripting environment in Python and TCL
• Building and maintaining the Embedded-Linux distribution (using Yocto), as well as writing the Linux-Drivers of the Programmable-Logic units
• Conducting extensive hands-on in-lab testing using Xilinx Chipscope and electronic test instruments (oscilloscope, logic-analyzer etc.)
• Functioning as a mentor to other FPGA engineers in the Institute, providing professional guidance, review and assistance with debugging of complex issues.
• Performing a wide range of technical duties on a regular basis, from writing documentations and user manuals for both HW and SW to coordinating effectively with Firmware, PCB and System teams etc
Embedded Entwicklung / hardwarenahe Entwicklung, Embedded Linux, Field Programmable Gate Array (FPGA), Xilinx (allg.), C++, Python, TCL/TK
2/2015 – 8/2015
Tätigkeitsbeschreibung
• Responsible for the prototyping of a high-speed Imaging IP on a Xilinx Virtex7-2000 FPGA.
• Involved in the prototyping of other IPs using the HAPS-60 and HAPS-70 prototyping platforms.
Field Programmable Gate Array (FPGA), Verilog HDL, Xilinx (allg.), Python, TCL/TK
8/2012 – 2/2015
Tätigkeitsbeschreibung
• Supervising a team of 3 FPGA engineers in the development of intel® RealSence™ 3D Camera's FPGA prototyping system to a tight deadline (MIPI D-Phy interface)
• Overseeing the meticulous definition and review of design constraints to achieve timing closure on a high-speed multiple asynchronous clock domains design
• Directing all activities associated with the partition of the ASIC design into 2 Xilinx Virtex7 FPGA boards, whilst designing additional Xilinx Spartan6 FPGA systems for the camera's testing boards
• Prototyping of the 2D-Camera imaging IP on HAPS-70 platforms (MIPI C-Phy interface)
• Successfully registering a reduction in debug count as well as increasing QOR via the integration of the FPGA design into the ASIC's UVM verification environment
Field Programmable Gate Array (FPGA), Verilog HDL, Xilinx (allg.), Python, TCL/TK
1/2007 – 8/2012
Tätigkeitsbeschreibung
• Presiding over the analysis and routing of SATA communication between multiple storage systems as part of the high speed Xilinx Virtex5 FPGA system design
• Overseeing the successful completion of several other projects on Altera FPGA’s
• Managing the end to end development of Embedded software
• Developing for numerous microcontroller types (ARM Cortex, Cygnal, TI, DSPic etc) and in numerous design environments (Keil, IAR, TI CodeComposer, Eclipse etc.)
• Performing reverse engineering of embedded software
Altera (allg.), Embedded Entwicklung / hardwarenahe Entwicklung, Field Programmable Gate Array (FPGA), ModelSim (Mentor Graphics), Verilog HDL, VHDL (VHSIC Hardware Description Language), Xilinx (allg.), Python
Ausbildung
Haifa, Israel
Über mich
Weitere Kenntnisse
* Languages: C, Assembly, Matlab
* Scripting: Python, TCL
* FPGA: Xilinx, Altera
* Design tools: Xilinx Vivado&IDE, Altera Quartus,Synopsys Synplify-Premier, Certify, ProtoCompiler
* Simulation: Modelsim, VCS, Verdi
* Revision Control: SVN, Git
*OS: Linux, Windows, Embedded Linux (Yocto)
* Microcontrollers: ARM, Cygnal, TI, DSPic etc.
* Reverse Engineering: IDA pro, OllyDbg
Persönliche Daten
- Deutsch (Gut)
- Englisch (Fließend)
- Hebräisch (Muttersprache)
- Europäische Union
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