FPGA and Embedded Software Design Engineer

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Suite 21 Edinburgh
13.10.2020

Kurzvorstellung

A. S. is a software engineer with 10 years of experience on ASIC, FPGA, embedded software andfirmware. He has worked both as an employee and as a consultant in various market fields from telecommunications to robotics.

Auszug Referenzen (3)

"Grasps concepts very quickly and demonstrates a high level of effort to reach the goals. Showed great support at the closing stages of the project."
Robotics senior software engineer
Anthony Wilson
Tätigkeitszeitraum

10/2018 – 3/2020

Tätigkeitsbeschreibung

● 3D image modules API bring-up
● Object recognition and path planning algorithms development in C++
● Results visualisation functionality development
● Mapping and localisation algorithms research and development
● 3D surface capture development

Eingesetzte Qualifikationen

Embedded Linux, simultaneous localization and mapping (SLAM), C++


"A. is a friendly, knowledgeable, experienced engineer who is quick to understand requirements and start adding value and implementing solutions."
Senior software design engineer
Ian Jeffray
Tätigkeitszeitraum

9/2017 – 10/2017

Tätigkeitsbeschreibung

● Firmware development for the implementation of MD5-hash based verification of product registration.
● Firmware development for the implementation of balanced use of the nitrogen generator sub-compartments.

Eingesetzte Qualifikationen

Firmware


"A. did a great job in designing, implementing and verifying the software and firmware, interfacing with RTL design, and supporting the HW team."
Embedded Software Engineer
Kundenname anonymisiert
Tätigkeitszeitraum

1/2014 – 3/2017

Tätigkeitsbeschreibung

LiFi integration in Broadcom SoC
● ASIC architecture definition
● Integration process definition
● IP buses width, bandwidth, role and end point definition
● Verification process definition
● FPGA non-synthesizable components replacement with RTL blocks

Li-Fi-X
● Cypress FX2 device USB firmware development
● RTL FIFO design for Cypress FX2
● LatticeMicro32 soft-core integration
● Complete USB to WiFi stack development on Linux driver
● Android drivers complete development and technology integration
● Embedded linux kernel customization
● Complete USB to WiFi stack development on Windows driver
● Complete USB to WiFi stack development on MacOS driver
● 802.11i encryption/decryption algorithms development
● User-space applications configuration tool development
● Verification of the final solution

Li-Flame
● LiFi RTL IP multiple access and handover functionality addition
● Soft-core firmware modification for multiple access and handover
● Linux network drivers development and kernel customization
● User-space application configuration tool development
● Windows driver development
● Verification of the final solution

10Mbps Li-Fi Connectivity Solution
● External RTL IP repurpose from WiFi to LiFi
● FPGA soft-core assembler design
● FPGA soft-core firmware design
● RTOS development on TI DSP/BIOS
● DSP filtering implementation
● Embedded lInux driver development.
● User-space applications development.
● FPGA code modification for throughput increase.
● System verification

Eingesetzte Qualifikationen

Embedded Linux, Field Programmable Gate Array (FPGA), Verilog HDL, VHDL (VHSIC Hardware Description Language), Vivado (Xilinx), Kernel Programmierung, OSX, Firmware

Ich biete

  • Device drivers
  • Echtzeitbetriebssystem (RTOS)
  • Embedded Linux
  • FPGA
  • FreeRTOS
  • Telnet (Telecommunication Network)
  • UVM
  • Verilog
  • VHDL

Projekt‐ & Berufserfahrung

System design lead and FPGA designer
Rinicom Ltd, London
6/2019 – 9/2019 (4 Monate)
Telekommunikation
Tätigkeitszeitraum

6/2019 – 9/2019

Tätigkeitsbeschreibung

● System architecture definition
● Telecommunications protocol definition
● RTL architecture review and additions proposal
● MAC firmware review

Eingesetzte Qualifikationen

Field Programmable Gate Array (FPGA), Verilog HDL, VHDL (VHSIC Hardware Description Language), Firmware


Robotics senior software engineer
QLTech Ltd, Aberdeen
10/2018 – 3/2020 (1 Jahr, 6 Monate)
Öl- und Gasindustrie
Tätigkeitszeitraum

10/2018 – 3/2020

Tätigkeitsbeschreibung

● 3D image modules API bring-up
● Object recognition and path planning algorithms development in C++
● Results visualisation functionality development
● Mapping and localisation algorithms research and development
● 3D surface capture development

Eingesetzte Qualifikationen

Embedded Linux, simultaneous localization and mapping (SLAM), C++


System design lead and FPGA designer
TethIR Ltd, London
4/2018 – 2/2019 (11 Monate)
Telekommunikation
Tätigkeitszeitraum

4/2018 – 2/2019

Tätigkeitsbeschreibung

● System architecture definition
● RTL FPGA code development on Zynq
● Synchronization block development in Matlab and Verilog
● Zynq ARM processor configuration
● ARM Cortex R5 firmware development
● Petalinux development

Eingesetzte Qualifikationen

Field Programmable Gate Array (FPGA), Verilog HDL, VHDL (VHSIC Hardware Description Language)


Senior software engineer
IMV Technology Ltd, Strathclyde Business Park, Phoenix Cres, Bellshill
11/2017 – 4/2018 (6 Monate)
High-Tech- und Elektroindustrie
Tätigkeitszeitraum

11/2017 – 4/2018

Tätigkeitsbeschreibung

Equine ultrasound probe
● Beamformer RTL IP repurpose for higher resolution and smaller depth
● Product IDs functionality addition in firmware

Easi-Scan Go
● Beamformer RTL IP design
● Altera Cyclone V ARM Linux kernel compilation flow development
● Device tree source development
● Filesystem compilation flow development
● Boot image development
● Firmware design

Eingesetzte Qualifikationen

Embedded Linux, Field Programmable Gate Array (FPGA), Verilog HDL, Firmware


Senior software design engineer
A2E Ltd, Alba Innovation Centre, Alba Campus, Livingston EH
9/2017 – 10/2017 (2 Monate)
High-Tech- und Elektroindustrie
Tätigkeitszeitraum

9/2017 – 10/2017

Tätigkeitsbeschreibung

● Firmware development for the implementation of MD5-hash based verification of product registration.
● Firmware development for the implementation of balanced use of the nitrogen generator sub-compartments.

Eingesetzte Qualifikationen

Firmware


Senior software engineer
A2E Ltd, Alba Innovation Centre, Alba Campus, Livingston EH
9/2017 – 10/2017 (2 Monate)
High-Tech- und Elektroindustrie
Tätigkeitszeitraum

9/2017 – 10/2017

Tätigkeitsbeschreibung

● Study and implementation specification of a High-Level-Data-Link (HDLC) MAC and LLC engine.
● Implementation of the HDLC firmware component for both station and access points.
● Verification of the HDLC firmware against third party electrical meter and virtual DLMS server

Eingesetzte Qualifikationen

Embedded Linux, HDLC (High-Level Data Link Control)


Senior software design engineer
A2E Ltd, Alba Innovation Centre, Alba Campus, Livingston EH
6/2017 – 6/2017 (1 Monat)
High-Tech- und Elektroindustrie
Tätigkeitszeitraum

6/2017 – 6/2017

Tätigkeitsbeschreibung

● Studied existing code and existing limitations for porting solution to Windows 10
● Proposed solution via the development of a Windows 10 printer driver installer
● Implemented Windows 10 driver installer software

Eingesetzte Qualifikationen

Kernel Programmierung


Senior software design engineer
A2E Ltd, Alba Innovation Centre, Alba Campus, Livingston EH
5/2017 – 8/2017 (4 Monate)
High-Tech- und Elektroindustrie
Tätigkeitszeitraum

5/2017 – 8/2017

Tätigkeitsbeschreibung

● FPGA design from scratch of a system interfacing to 3 different peripherals, one MCU and an external memory module.
● FPGA / MCU communication verification with firmware design engineer
● FPGA design bring-up against hardware module.

Eingesetzte Qualifikationen

Field Programmable Gate Array (FPGA), Verilog HDL, Firmware


Senior software design engineer
A2E Ltd, Alba Innovation Centre, Alba Campus, Livingston EH
3/2017 – 11/2017 (9 Monate)
High-Tech- und Elektroindustrie
Tätigkeitszeitraum

3/2017 – 11/2017

Tätigkeitsbeschreibung

Subsea Electronic Module controlled via PLC over PROFINET

● PROFINET protocol study and implementation planning
● Firmware and FPGA architecture specification and development roadmap
● Firmware development for HSCAN, FTCAN, serial I2C, and SPI peripherals
● Firmware integration into FreeRTOS
● FPGA design and verification
● PLC - field device interface bring-up and GSD development

Eingesetzte Qualifikationen

Field Programmable Gate Array (FPGA), Verilog HDL, VHDL (VHSIC Hardware Description Language), Firmware


Verilog and CPLD Developer
Elmen Consultants Ltd, Remote
1/2015 – 8/2015 (8 Monate)
High-Tech- und Elektroindustrie
Tätigkeitszeitraum

1/2015 – 8/2015

Tätigkeitsbeschreibung

SPI to SDRAM Interface.
● Solution architecture specification
● Project management
● Verilog Design
● CPLD Implementation and Verification
● Creation of demo for client

SPI to SRAM Interface
● Solution architecture specification
● Project management
● Verilog Design
● CPLD Implementation and Verification
● Creation of demo for client

Eingesetzte Qualifikationen

ModelSim (Mentor Graphics), Quartus (Altera), Verilog HDL


Embedded Software Engineer
pureLiFi Ltd, 9 Haymarket Terrace, Edinburgh EH12 5EZ
1/2014 – 3/2017 (3 Jahre, 3 Monate)
Telekommunikation
Tätigkeitszeitraum

1/2014 – 3/2017

Tätigkeitsbeschreibung

LiFi integration in Broadcom SoC
● ASIC architecture definition
● Integration process definition
● IP buses width, bandwidth, role and end point definition
● Verification process definition
● FPGA non-synthesizable components replacement with RTL blocks

Li-Fi-X
● Cypress FX2 device USB firmware development
● RTL FIFO design for Cypress FX2
● LatticeMicro32 soft-core integration
● Complete USB to WiFi stack development on Linux driver
● Android drivers complete development and technology integration
● Embedded linux kernel customization
● Complete USB to WiFi stack development on Windows driver
● Complete USB to WiFi stack development on MacOS driver
● 802.11i encryption/decryption algorithms development
● User-space applications configuration tool development
● Verification of the final solution

Li-Flame
● LiFi RTL IP multiple access and handover functionality addition
● Soft-core firmware modification for multiple access and handover
● Linux network drivers development and kernel customization
● User-space application configuration tool development
● Windows driver development
● Verification of the final solution

10Mbps Li-Fi Connectivity Solution
● External RTL IP repurpose from WiFi to LiFi
● FPGA soft-core assembler design
● FPGA soft-core firmware design
● RTOS development on TI DSP/BIOS
● DSP filtering implementation
● Embedded lInux driver development.
● User-space applications development.
● FPGA code modification for throughput increase.
● System verification

Eingesetzte Qualifikationen

Embedded Linux, Field Programmable Gate Array (FPGA), Verilog HDL, VHDL (VHSIC Hardware Description Language), Vivado (Xilinx), Kernel Programmierung, OSX, Firmware


Digital Design Engineer
ST Microelectronics Ltd, 33 Pinkhill, Edinburgh, EH12 7BF
12/2012 – 12/2013 (1 Jahr, 1 Monat)
High-Tech- und Elektroindustrie
Tätigkeitszeitraum

12/2012 – 12/2013

Tätigkeitsbeschreibung

BSI 8MP camera sensor
● Port of the existing verification platform to a UVM based verification.
● Creation of IP-level UVM test-benches for other members.
● Support in UVM verification for all the members in the team.
● Merge of the analogue mixed signal flow to the UVM test-bench for higher usability.
● Embedded software design in C for sensor setup and control for 8051.
● Image compression encoding block design
● Status line controller block design
● Analogue / digital interface development
● AMS verification support
● csh scripting
● Main responsible for the sensor verification

Proximity / ALS sensor development revision 1.1
● Main verification responsible for RTL and netlist creation
● AMS verification support
● Embedded software design in custom assembly covering new functionalities

8MP camera sensor
● Analysis of the system architecture to be deployed
● AMS verification support
● UVM Verification platform creation for the complete system.
● Synthesis of blocks and checks for timing constraints.
● Blocks creation with Catapult-C
● Acquaintance of younger members with the UVM flow.

Proximity / ALS sensor development revision 1.0
● Support verification of the sensor before the tape-out.
● Python scripts for regression automation.

Eingesetzte Qualifikationen

Field Programmable Gate Array (FPGA), Verilog HDL


Graduate Design Engineer
Imagination Technologies Group plc, Imagination House Home Park Estate, Kings Langley
10/2010 – 12/2012 (2 Jahre, 3 Monate)
High-Tech- und Elektroindustrie
Tätigkeitszeitraum

10/2010 – 12/2012

Tätigkeitsbeschreibung

LTE Turbo Encoder / Decoder IP
● Analysis of architecture for a customizable LTE error correction unit.
● Design in Verilog.
● Design of bit-accurate model in Matlab.
● Verification was done both on FPGA and in Modelsim
● Patented low – area / power implementation of the interleaver / de-interleaver blocks.
● Linux driver development for PCI cards.
● Linux driver development and embedded software development for device USB bundle.

802.11 WLAN Decoder
● Perl script design for translation of Verilog blocks to VHDL.
● Design of AMBA bus.
● Designed blocks for FPGA in order to facilitate communication of the system with the host via USB.
● DSP processor DMA and filtering blocks implementation

DVBT Decoder
● Design of IIR filtering blocks.
● Generic FIFO
● Verification and debug of protocols on FPGA

MIMO -WLAN Decoder
● Updated signal conditional blocks for support of antenna with wider band and worse SNR.
● Fine-tuned software and hardware blocks operation in order to meet power constraints. Netlist simulations and power profiling was done with Palladium tools. Exact power measurements were done with PrimeTime PX.
● Supporting UVM team in order to resolve issues in the system.
● Designed new blocks supporting MIMO WLAN protocol.
● Working with the SystemC team in order to resolve issues in mismatch between model and RTL in our DSP., DMA and Viterbi blocks.
● Supporting verification team by providing bit-streams for multi-FPGA projects. Synthesis was done with a combination of Certify, Synplify – Pro and Xilinx ISE flow.

Eingesetzte Qualifikationen

Field Programmable Gate Array (FPGA), Verilog HDL, VHDL (VHSIC Hardware Description Language)


Ausbildung

MEMS Master
(University of Edinburgh)
Jahr: 2017
Ort: Edinburgh, UK

Diploma in Electrical engineering and computer's technology
(7.5)
Jahr: 2010
Ort: University of Patras, Greece

Qualifikationen

MEMS Master of Science University of Edinburgh (2014-2017). Completed with distinction

Diploma in Electronics from the University of Patras (2005 - 2010). Completed with 7.5/10.

Persönliche Daten

Sprache
  • Englisch (Fließend)
  • Französisch (Gut)
  • Deutsch (Grundkenntnisse)
  • Italienisch (Grundkenntnisse)
  • Griechisch (Muttersprache)
Reisebereitschaft
Europa
Arbeitserlaubnis
  • Europäische Union
Home-Office
unbedingt
Profilaufrufe
618
Alter
33
Berufserfahrung
10 Jahre und 5 Monate (seit 08/2010)
Projektleitung
1 Jahr

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