freiberufler Senior FPGA/ASIC/SoC Expert, Functional Verification, Embedded SW-Development, Algorithm Design (Image Processing, Mobile Communications), Project Management, Test Management, Functional Safety (ISO 26262) auf freelance.de

Senior FPGA/ASIC/SoC Expert, Functional Verification, Embedded SW-Development, Algorithm Design (Image Processing, Mobile...

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  • 105€/Stunde
  • Bayern
  • Weltweit
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  • 02.03.2024

Kurzvorstellung

With more than 20 years professional experience and 15 years as FPGA expert and firmware developer my strengths are in architecture and implementation of efficient data processing (CV, digital comm., machine learning) and high-speed interfacing.

Qualifikationen

  • ARM-Architektur
  • Automotive functional safety professional (AFSP)
  • Embedded Systems
  • Enterprise Architect (EA)
  • Field Programmable Gate Array (FPGA)
  • ISO 26262
  • ModelSim (Mentor Graphics)
  • Python
  • Technisches Projektmanagement
  • VHDL (VHSIC Hardware Description Language)
  • Vivado (Xilinx)
  • Xilinx (allg.)

Projekt‐ & Berufserfahrung

FPGA/SoC Architect, FPGA/SoC Lead Engineer
Kundenname anonymisiert, Mannheim/Bremen
9/2023 – offen (7 Monate)
Automobilindustrie
Tätigkeitszeitraum

9/2023 – offen

Tätigkeitsbeschreibung

FPGA Architecture of low latency and high speed ASIL-D image processing SoC.
FPGA Architecture, multi-camera image processing and sensor fusion to environmental model, high-speed interfacing, ISO 26262), Xilinx Zynq Ultrascale+ MPSoC

Eingesetzte Qualifikationen

VHDL (VHSIC Hardware Description Language), Vivado (Xilinx), ARM-Architektur, ISO 26262

Senior FPGA Developer
Defence Electronics Supplier, Fürth
11/2022 – 7/2023 (9 Monate)
Defence
Tätigkeitszeitraum

11/2022 – 7/2023

Tätigkeitsbeschreibung

Resource efficient real-time Rectifier Algorithm for small FPGA
Algorithm development, VHDL implementation, Verification

Eingesetzte Qualifikationen

Field Programmable Gate Array (FPGA), ModelSim (Mentor Graphics), Python, VHDL (VHSIC Hardware Description Language)

Senior FPGA Developer
Vector Informatik GmbH, Stuttgart
6/2021 – 3/2022 (10 Monate)
Automobilindustrie
Tätigkeitszeitraum

6/2021 – 3/2022

Tätigkeitsbeschreibung

Efficient real-time Zstd Compression Algorithm Module for small FPGA
Concept, design and implementation of a ZSTD compressor IP Core using VHDL and Python

Eingesetzte Qualifikationen

Field Programmable Gate Array (FPGA), Python, VHDL (VHSIC Hardware Description Language)

FPGA/SoC Architect, FPGA/SoC Lead Engineer
Wavelight GmbH, Erlangen
6/2021 – offen (2 Jahre, 10 Monate)
Life Sciences
Tätigkeitszeitraum

6/2021 – offen

Tätigkeitsbeschreibung

FPGA Architecture of large image processing SoC
FPGA Architecture, high-speed image processing and sensor fusion, high-speed interfacing, IEC62304 (Medical Engineering), Xilinx Zynq SoC

Eingesetzte Qualifikationen

Field Programmable Gate Array (FPGA), ModelSim (Mentor Graphics), VHDL (VHSIC Hardware Description Language), Vivado (Xilinx), Xilinx (allg.), Enterprise Architect (EA), Python

FPGA Architect, VHDL Developer, Embedded SW Developer
LEICA Geosystems AG, Heerbrugg
1/2020 – 10/2020 (10 Monate)
High-Tech- und Elektroindustrie
Tätigkeitszeitraum

1/2020 – 10/2020

Tätigkeitsbeschreibung

FPGA architecture and implementation of LIDAR and multi-camera-based 3D environment scanner
Design, implementation and verification of image processing and sensor fusion modules
High-speed interfacing
Linux device driver adaption

Eingesetzte Qualifikationen

Embedded Entwicklung / hardwarenahe Entwicklung, Field Programmable Gate Array (FPGA), Microsemi (allg.), VHDL (VHSIC Hardware Description Language), C++, Python

FPGA Architect, VHDL Developer, UVM Verification, Embedded SW Developer
LEICA Geosystems AG, Heerbrugg
12/2018 – 12/2019 (1 Jahr, 1 Monat)
High-Tech- und Elektroindustrie
Tätigkeitszeitraum

12/2018 – 12/2019

Tätigkeitsbeschreibung

FPGA architecture and implementation of lidar, camera and IMU (SLAM) based 3D environment scanner, adaption of Linux device drivers

Eingesetzte Qualifikationen

Embedded Linux, Field Programmable Gate Array (FPGA), Microsemi (allg.), Verilog HDL, VHDL (VHSIC Hardware Description Language)

FPGA Architect, VHDL Developer
Kundenname anonymisiert, Backnang
6/2018 – 11/2018 (6 Monate)
Maschinen-, Geräte- und Komponentenbau
Tätigkeitszeitraum

6/2018 – 11/2018

Tätigkeitsbeschreibung

FPGA architecture and implementation of welding current source controlling FPGA

Eingesetzte Qualifikationen

Field Programmable Gate Array (FPGA)

Product Manager, SW Developer
CMORE Automotive GmbH, Lindau
1/2018 – 7/2018 (7 Monate)
Automobilindustrie
Tätigkeitszeitraum

1/2018 – 7/2018

Tätigkeitsbeschreibung

Design and development of Python 3 and Oracle based testsuite for automotive training data annotation tools

Eingesetzte Qualifikationen

Oracle Database, Python

Python / C++ Software Developer
Kundenname anonymisiert, Stuttgart
9/2017 – 4/2018 (8 Monate)
Luft- und Raumfahrtindustrie
Tätigkeitszeitraum

9/2017 – 4/2018

Tätigkeitsbeschreibung

Test system for production end-of-line tests of cryptographic UDP/TCC/IP packet filters (firewall)
Concept of end of line testing
Python implementation of test system
Test engineering

Eingesetzte Qualifikationen

Testdesign (IT), Python

Senior FPGA Consultant
Checkpoint Software Technologies Ltd., Stuttgart
8/2017 – 9/2017 (2 Monate)
High-Tech- und Elektroindustrie
Tätigkeitszeitraum

8/2017 – 9/2017

Tätigkeitsbeschreibung

Design of suitable stereo image processing algorithms and system on a chip (SoC) system architecture

Eingesetzte Qualifikationen

Field Programmable Gate Array (FPGA), Vivado (Xilinx), Computer Vision, MATLAB / Simulink, Embedded Software Engineering

Project Manager (Customer: Daimler AG)
CMORE Automotive GmbH, Lindau
7/2017 – 11/2018 (1 Jahr, 5 Monate)
Automobilindustrie
Tätigkeitszeitraum

7/2017 – 11/2018

Tätigkeitsbeschreibung

Customer Project Management of international data annotation project

Eingesetzte Qualifikationen

Projektleitung / Teamleitung (IT)

Project Manager (Customer: VALEO)
CMORE Automotive GmbH, Lindau
5/2017 – 8/2017 (4 Monate)
Automobilindustrie
Tätigkeitszeitraum

5/2017 – 8/2017

Tätigkeitsbeschreibung

Project Management for large international Team (3 Locations, 120 employees)

Eingesetzte Qualifikationen

Projektleitung / Teamleitung (IT)

VHDL Developer
Kundenname anonymisiert, Karlsruhe
3/2017 – 8/2017 (6 Monate)
Automobilindustrie
Tätigkeitszeitraum

3/2017 – 8/2017

Tätigkeitsbeschreibung

Integration of LL-JPEG Encoder in VHDL frame grabber design
FPGA Test Framework

Eingesetzte Qualifikationen

Field Programmable Gate Array (FPGA), Microsemi (allg.), Computer Vision

FPGA Architect, VHDL Developer, Embedded SW Developer
SMR Automotive Mirrors Stuttgart GmbH, Stuttgart
4/2016 – 3/2017 (1 Jahr)
Automobilindustrie
Tätigkeitszeitraum

4/2016 – 3/2017

Tätigkeitsbeschreibung

Architecture of algorithmic SoC in multi-camera based ADAS System
ADAS multi vision algorithm design and implementation
FPGA test framework

Eingesetzte Qualifikationen

Field Programmable Gate Array (FPGA), Vivado (Xilinx), C++, Python, Automotive functional safety professional (AFSP), Embedded Software Engineering, ISO 26262

Algo Test Manager
ADC GmbH, Continental AG, Lindau
4/2015 – 7/2016 (1 Jahr, 4 Monate)
Automobilindustrie
Tätigkeitszeitraum

4/2015 – 7/2016

Tätigkeitsbeschreibung

Radar Algorithm Test Management
Code Reviews, Test Reviews, Verification Planning, Validation (1mio km) planning, Issue Tracking, Test Coverage, Requirements Coverage, Algo Integration Tests, Static/Dynamic White and Black Box Tests, Test Metrics, Functional Safety Validation (ISO 26262)

Eingesetzte Qualifikationen

Testdesign (IT), Testmanagement / Testkoordination (IT), Python, ISO 26262

FPGA Architect, VHDL Developer, BFM Verification
ADC GmbH, Continental AG, Lindau
9/2012 – 3/2015 (2 Jahre, 7 Monate)
Automobilindustrie
Tätigkeitszeitraum

9/2012 – 3/2015

Tätigkeitsbeschreibung

FPGA / ASIC Implementation of Stereo Image Camera based Driver Assistance Sensor
Stereo Vision algorithm design
C++ SW reference model implementation
VHDL testbench framework
HW emulation
Implementation and test of safety mechanisms

Eingesetzte Qualifikationen

Field Programmable Gate Array (FPGA), VHDL (VHSIC Hardware Description Language), Xilinx ISE (Integrated Synthesis Environment), MATLAB / Simulink

FPGA Architect, VHDL Developer, BFM Verification
ADC GmbH, Continental AG, Lindau
9/2011 – 8/2012 (1 Jahr)
Automobilindustrie
Tätigkeitszeitraum

9/2011 – 8/2012

Tätigkeitsbeschreibung

FPGA implementation of stereo vision ADAS camera sensor modules
Software reference model implementation
BFM testbench framework
Testcase definition and VHDL implementation
Module and regression tests

Eingesetzte Qualifikationen

VHDL (VHSIC Hardware Description Language), Xilinx ISE (Integrated Synthesis Environment), C++, MATLAB / Simulink

FPGA Architect, FPGA Developer, Algorithm Developer
Alcatel Lucent Deutschland AG, Stuttgart
8/2010 – 7/2011 (1 Jahr)
High-Tech- und Elektroindustrie
Tätigkeitszeitraum

8/2010 – 7/2011

Tätigkeitsbeschreibung

Model based design of FPGA GSM/UMTS mobile communication modules
Digital communication algorithm design (OFDM, PSK, GSM, UMTS)

Eingesetzte Qualifikationen

MATLAB / Simulink, Nachrichtentechnik

Single Carrier Mobile Communication Algorithm Developer, FPGA Developer
Thales Deutschland GmbH, Defense and Security Syst, Pforzheim
12/2009 – 7/2010 (8 Monate)
High-Tech- und Elektroindustrie
Tätigkeitszeitraum

12/2009 – 7/2010

Tätigkeitsbeschreibung

Specification and implementation of a SoC HW/SW-Controller
Software defined radio
Model-based design
Algorithm design
FPGA implementation
Requirements engineering

Eingesetzte Qualifikationen

Field Programmable Gate Array (FPGA), VHDL (VHSIC Hardware Description Language), MATLAB / Simulink, Requirement Analyse, Nachrichtentechnik

FPGA Architect, VHDL Developer, Algorithm Design
Sony Deutschland GmbH, Stuttgart
5/2007 – 11/2009 (2 Jahre, 7 Monate)
High-Tech- und Elektroindustrie
Tätigkeitszeitraum

5/2007 – 11/2009

Tätigkeitsbeschreibung

Design and implementation of MIMO Powerline OFDM communication system
Algorithm design (OFDM channel estimation)
Model-based algorithm design
FPGA Implementation

Eingesetzte Qualifikationen

Field Programmable Gate Array (FPGA), Xilinx ISE (Integrated Synthesis Environment), C++, Linux Entwicklung, MATLAB / Simulink, Python, Nachrichtentechnik

Ausbildung

Developing with Embedded Linux
Ausbildung
2020
Online
C++ Programming For Embedded Systems
Ausbildung
2020
Online
TÜV Rheinland Functional Safety Engineer (Automotive ISO 26262)
Ausbildung
2016
Kornwestheim
Certified Project Management Associate IPMA Level D
Ausbildung
2010
Stuttgart
Elektrotechnik und Informationstechnik
Diplom Ingenieur (TH)
2002
Stuttgart

Über mich

With more than 20 years of professional experience and about 15 years as FPGA expert and firmware developer, a proven track record of my work can be found in many real-world products.

Amongst others:

High speed imaging
What I did: FPGA Architecture Lead of distributed multi SoC system, high-speed interfacing, image processing pipelines, scheduling, verification, reviews
Products: NextGenRS – Next Generation Refractive Surgery (WaveLight GmbH, Erlangen)

LIDAR, multi-camera and IMU sensor fusion
What I did: FPGA Architecture (LVDS, AMBA bus (AXI4, AHBL, APB3), MIPI CSI-2 camera interfacing, image processing pipelines), scheduling, high-speed interfacing, verification, embedded SW development, adaption of Linux device drivers
Products: e.g. BLK2Go / BLK247 / BLKNow (Leica Geosystems AG, Schweiz)

High level synthesis of OpenCV library to be available on FPGA
What I did: Optimization and consultation, development partnership
Products: AuvizCV IP Core Library (Xilinx Inc.)

SoC multi camera image processing (features, stitching)
What I did: Architecture (Mipi, AXI4), image processing algorithm design (Matlab/C++ to VHDL), SoC implementation, embedded Linux device driver development
Products: e.g. SMR ECU Gen 2 (SMR Samvardhana Motherson Reflectec GmbH, Stuttgart)

FPGA/ASIC stereo vision (rectification, optical flow, disparity maps, feature/object detection)
What I did: Architecture, scheduling, algorithm implementation (C++ to VHDL), verification
Products: e.g. MFC 300/430 Multi-Function Stereo Camera (Continental AG, Lindau)

LTE, UMTS and GSM EDGE mobile communication OFDM MIMO baseband
What I did: Algorithm design, model-based FPGA implementation (Xilinx System Generator), verification
Products: Proof of concepts, demonstrators (Alcatel Lucent, Sony)

Persönliche Daten

Sprache
  • Deutsch (Muttersprache)
  • Englisch (Fließend)
  • Französisch (Grundkenntnisse)
Reisebereitschaft
Weltweit
Arbeitserlaubnis
  • Europäische Union
  • Schweiz
Home-Office
bevorzugt
Profilaufrufe
2876
Berufserfahrung
21 Jahre und 2 Monate (seit 01/2003)
Projektleitung
2 Jahre

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