FPGA Entwicklung (DO-254)

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87719 Mindelheim
18.02.2021

Kurzvorstellung

Freelance Hardware Engineer specialized in aerospace technologies (all safety Levels).

Ich biete

  • Field Programmable Gate Array (FPGA)
  • Hardware Entwicklung
  • Luft- und Raumfahrttechnik (allg.)
  • VHDL (VHSIC Hardware Description Language)

Projekt‐ & Berufserfahrung

FPGA Designer
XiAn Aviation Brake Technology Co., Ltd., Xi'an - Munich
9/2017 – offen (3 Jahre, 7 Monate)
Luft- und Raumfahrtindustrie
Tätigkeitszeitraum

9/2017 – offen

Tätigkeitsbeschreibung

MA700 Brake Control System Project
- Development of the I/O FPGA according to the defined processes (requirements capture, conceptual design and detailed design).
- Verification of the Monitor FPGA according to the defined processes (verification cases and verification procedures).

Eingesetzte Qualifikationen

Field Programmable Gate Array (FPGA), Luft- und Raumfahrttechnik (allg.)


Hardware Design Engineer
DIEHL Aerospace, Ueberlingen
7/2015 – 12/2015 (6 Monate)
Luft- und Raumfahrtindustrie
Tätigkeitszeitraum

7/2015 – 12/2015

Tätigkeitsbeschreibung

Research Project I/O Board for Remote Control Electronics
- Selection and Integration of all the modules to create the I/O B oard schematic.
- Design of the I/O FPGA to interface with the CPU Board:
* Requirements capture for the FPGA.
* Migration of all algorithms previously implemented in external DSPs into the FPGA
* Design and implementation of the FPGA (SmartFusion2, VHDL, Synplify)
* Performing the simulation (writing the test bench and simulation models) using ModelSim to verify the design.

- Update of the S2P FPGA in the CPU Board to interface with the I/O Board:
* Requirements capture for the FPGA.
* Migration of all algorithms previously implemented in external DSPs into the FPGA
* Design and implementation of the FPGA ( ProASIC3 , VHDL,
* Performing the simul ation (writing the test bench and simulation models) using ModelSim to verify the design.

Eingesetzte Qualifikationen

Field Programmable Gate Array (FPGA), Hardware Entwicklung, VHDL (VHSIC Hardware Description Language), Luft- und Raumfahrttechnik (allg.)


Hardware Senior Consultant
Qingan Group Co., Ltd., Xi'an - Munich
3/2015 – offen (6 Jahre, 1 Monat)
Luft- und Raumfahrtindustrie
Tätigkeitszeitraum

3/2015 – offen

Tätigkeitsbeschreibung

MA700 High Lift System Project
- Definition of the hardware related tasks to perform during the complete project and estimation of the needed time to complete.
- Definition of the development life cycle processes to ensure DO 254 compliance i.e. writing the required plans and standards
- Development of the I/O FPGA according to the defined processes (requirements capture, conceptual design and detailed design).
- Development of the Monitor FPGA according to the defined processes (requirements capture, conceptual design and detailed design).
- Requirements capture for the FMCM FPGA according to the defined processes and standards.

Eingesetzte Qualifikationen

Field Programmable Gate Array (FPGA), Luft- und Raumfahrttechnik (allg.)


Hardware Senior Consultant
SAVIC, Xi'an - Munich
7/2013 – 5/2016 (2 Jahre, 11 Monate)
Luft- und Raumfahrtindustrie
Tätigkeitszeitraum

7/2013 – 5/2016

Tätigkeitsbeschreibung

C919 Cockpit Display System Project:
- DO 254 certification support.
- Requirements capture for the Mixer and Monitor FPGAs.
- Implementation of the Head Up Display (HUD) logic in the Mixer FPGA (IGLOO2,
* Reverse calculation of the alpha channel from the GPU video input.
* Real time bore-sighting of the Enhanced Video System (EVS) video input
* Real time scaling of the EVS video input using a bilinear algorithm.
* Real time brightness an d contrast adjustment of the EVS video input.
* Merging the GPU and the modified EVS video streams using alpha blending.

C919 AFDX Switch Project:
- DO-254 certification support.

Eingesetzte Qualifikationen

Field Programmable Gate Array (FPGA), VHDL (VHSIC Hardware Description Language), Luft- und Raumfahrttechnik (allg.)


Hardware Design Engineer
DIEHL Aerospace, Ueberlingen
6/2012 – 2/2014 (1 Jahr, 9 Monate)
Luft- und Raumfahrtindustrie
Tätigkeitszeitraum

6/2012 – 2/2014

Tätigkeitsbeschreibung

Feasibility study Fly by wire avionic systems for a helicopter:
- Definition of the hardware architecture to satisfy the customer requirements in terms of processing power, I/O capabilities, power dissipation, size, environmental, etc. for:
* the Central Processing Modules (CPM)
* the I/O Modules (IOM)
* the Actuator Control Modules (ACM for main and tail rotors)

Research Project - CPU Board for a dual lane Remote Control Electronics
- Schematic capture of the Central Processing Unit (MPC8349A, PCI, DDR2, Gbit Ethernet,
USB 2.0, ProASIC3, Stratix II, Flash, NVRAM, AFDX, CAN, ARINC 429, RS 232)
- Integration of all the modules to create the board schematic (PSU, CPU, DSP and I/ O).
- Constraining the PCB to ensure reliable operation (Cadence’s Allegro Design Entry HDL, SigExplorer)
- Perform ing the Signal Integrity analysis for the high speed and high load buses (DDR2, PCI, SigExplorer)
- Design of the Serial to Parallel (S2P) FPGA to interface the I/O with the CPU
* Requirements capture for the FPGA.
* Design and implementation of the FPGA (Microsemi ProASIC3, VHDL, Synplify)
* Performing the simulation (writing the tes t bench and simulation models) using ModelSim to verify the design.

Eingesetzte Qualifikationen

Field Programmable Gate Array (FPGA), Hardware Entwicklung, VHDL (VHSIC Hardware Description Language), Luft- und Raumfahrttechnik (allg.)


Hardware Design Engineer
Develeast SA, Roveredo
4/2010 – 12/2014 (4 Jahre, 9 Monate)
Luft- und Raumfahrtindustrie
Tätigkeitszeitraum

4/2010 – 12/2014

Tätigkeitsbeschreibung

Development of DO-254 IP Cores (DAL A) in VHDL:
- Development of IP Cores to DAL A according to the DO 254.
* MIL-STD-1553B
* CAN
* Ethernet (10/100/1000 Mbps)
* ARINC 429
* SDRAM Controller ; and more
- Requirements capture for FPGAs according to the DO 254 (DAL A) for several clients.
- Test specification definition for FPGAs according to the DO 254 (DAL A) for several clients.
- Development of test benches to verify FPGAs according to the DO 254 (DAL A) for several clients.
- Performing independent reviews on different design data (requirements, test specifications, FPGAs source code, etc.) according to the DO 254 (DAL A) for several clients.
- Support during the EASA certification audit (SOI#2 and SOI#3) for a product including the CAN IP Core.

Eingesetzte Qualifikationen

Field Programmable Gate Array (FPGA), VHDL (VHSIC Hardware Description Language), Luft- und Raumfahrttechnik (allg.)


Hardware Design Engineer
DIEHL Aerospace, Ueberlingen
4/2008 – 3/2010 (2 Jahre)
Luft- und Raumfahrtindustrie
Tätigkeitszeitraum

4/2008 – 3/2010

Tätigkeitsbeschreibung

Common Remote Data Concentrator (cRDC) for the A350 IMA Project:
- Suppor t during the EASA certification audits (SOI#2 and SOI#3).
- Support during Airbus audits (SOI preparation and CFAR)
- CPU Core:
* Requirements capture for the Central Processing Unit of the CRDC (MPC8349A, DDR2, ProASIC3, Stratix II, Flash, NVRAM, AFDX)
* Schema tic capture and PCB constrain s definition (Cadence’s Allegro Design Entry HDL, SigExplorer)
* Perform ing the Signal Integrity analysis for the high speed and high load buses (DDR2, PCI, SigExplorer)
* Software revision and help in integration to ensure correctness when accessing the hardware.
* Writing the documentation of all the stages of the process in accordance to the DO-254 Standard (DAL A) and the internal Quality Process.

- CAN/A429 ASIC:
* Requirements capture for the FPGA/ASIC (CAN, ARINC429, DOORS).
* Designing and implementation of the FPGA (Altera Stratix II, VHDL, QuartusII)
* Performing the Static Timing Analysis (Timing Designer, TimeQuest).
* Writing the documentation of all the stages of the process in accordance to the DO-254 Standard (DAL A) and the internal Quality Process.
* Prepare the reviews with Altera for the HardCopy design.

- S2P FPGA:
* Requirements capture for the FPGA (DOORS).
* Designing and implementation of the FPGA (ProASIC3, VHDL)
* Performing the Static Timing Analysis.
* Writing the documentation of all the stages of the process in accordance to the DO-254 Standard (DAL A) and the internal Quality Process.

- Mockup Miniboard:
* Requirements capture for a prototype board to test the system concept and
architecture containing a DSP and an FPGA (TMS3 20F2808, ProA SIC 3)
* Schematic entry and PCB constrain (Cadence’s Allegro Design Entry HDL,
SigExplorer)

Eingesetzte Qualifikationen

Field Programmable Gate Array (FPGA), Hardware Entwicklung, VHDL (VHSIC Hardware Description Language), Luft- und Raumfahrttechnik (allg.)


Hardware Design Engineer
Creative Electronic Systems SA, Genf
10/2007 – 4/2008 (7 Monate)
Luft- und Raumfahrtindustrie
Tätigkeitszeitraum

10/2007 – 4/2008

Tätigkeitsbeschreibung

Program and Technology details omitted as per client's request:
- Requirements capture for an FPGA included in a Primary Flight Control Unit.
- PCBs Signal Integrity study and improvements
- Design and implementation of the FPGA to DAL C
- Performing the Static Timing Analysis.
- Performing the simulation (writing the test bench and simulation models) to verify a different FPGA (DAL A).
- Writing the documentation of all the stages of the process in accordance to the DO-254 Standard (DAL A/DAL C) and the internal Quality Process.
- Support during the EASA certification audits (SOI#1, SOI#2, SOI#3 and SOI#4).

Eingesetzte Qualifikationen

Field Programmable Gate Array (FPGA), Hardware Entwicklung, VHDL (VHSIC Hardware Description Language), Luft- und Raumfahrttechnik (allg.)


Hardware Design Engineer
Barco, Kortrik
4/2007 – 9/2007 (6 Monate)
Luft- und Raumfahrtindustrie
Tätigkeitszeitraum

4/2007 – 9/2007

Tätigkeitsbeschreibung

- Requirements capture for the Data Output FPGA (DOORS).
- Design and implementation of the Data Output FPGA (ACTEL Pro ASIC 3, VHDL, Synplify)
- Static Timing Analysis of the design (Timing Designer,
- Performing the simulation (writing the test bench and simulation models) using ModelSim/Cadence NC VHDL to verify the Frame Grabber FPGA
- Writing the documentation of all the stages of the process in accordance to the DO-254 Standard ( DAL A) and the internal Quality Process.

Eingesetzte Qualifikationen

Field Programmable Gate Array (FPGA), VHDL (VHSIC Hardware Description Language), Luft- und Raumfahrttechnik (allg.)


Hardware Design Engineer
Vibro Meter SA, Fribourg
11/2006 – 4/2007 (6 Monate)
Luft- und Raumfahrtindustrie
Tätigkeitszeitraum

11/2006 – 4/2007

Tätigkeitsbeschreibung

AFDX Project:
- Writing the System Specifications of an FPGA to perform some of the AFDX (ARINC 664) related functions and its interface to an MPC5554.

ERIU Project:
- Writing the Specification and Requirements for the Engine Rating Interface Unit.
- Design and implementation of the FPGA and test benches (VHDL, Visual Elite, ModelSim, ISE, Cadence NC VHDL Simulator).
- Design of a Test Box to verify the product (Schematic entry).
- Writing the documentation of all the stages of the process in accordance with company standards and methodologies.

Eingesetzte Qualifikationen

Field Programmable Gate Array (FPGA), Hardware Entwicklung, VHDL (VHSIC Hardware Description Language), Luft- und Raumfahrttechnik (allg.)


Hardware Design Engineer
Vibro Meter S.A., Fribourg
9/2005 – 3/2007 (1 Jahr, 7 Monate)
Luft- und Raumfahrtindustrie
Tätigkeitszeitraum

9/2005 – 3/2007

Tätigkeitsbeschreibung

- Requirements capture for the Enhanced Vibration Processing Unit (eVPU) FPGA (Reqtify).
- Design and implementation of the (DAL B) FPGA (Xilinx Spartan3, VHDL, Visual Elite, Synplify)
- Static Timing Analysis and simulation (ModelS im/Cadence NC VHDL).
- Schematic design of the digital circuitry: DSP, FPGA, D/A, A/D, SDRAM, DDRAM, etc. (Cadence’s Allegro Design Entry HDL)
- Signal Integrity study of the PCB DDR & SDRAM interfaces and re designed them to improve performance (Cadence's SpectraQuest).
- Design of automatic on board tests (JTAG, assembly and C) for the PowerPC5200B and the TI C6713 DSP to ease prototype debugging and industrialization process.
- Design and implementation of an acquisition software on the TMS320C6713 SDK to test the suitability of t he A/D converters (ADS1271).
- Software revision and help in integration.
- Writing the documentation of all the stages of the process in accordance to the DO-254 Standard (DAL B) and the internal Quality Process.

Eingesetzte Qualifikationen

Field Programmable Gate Array (FPGA), Hardware Entwicklung, VHDL (VHSIC Hardware Description Language), Luft- und Raumfahrttechnik (allg.)


System Engineer
Indo S.A., Barcelona
7/2005 – 8/2005 (2 Monate)
Maschinen-, Geräte- und Komponentenbau
Tätigkeitszeitraum

7/2005 – 8/2005

Tätigkeitsbeschreibung

Definition of the technical solutions for a new product used to automatically recognize shape and drills in glasses using scanners technology and image processing.

Eingesetzte Qualifikationen

Embedded Entwicklung / hardwarenahe Entwicklung


Hardware Engineer
Selex Communications (former Marconi), Genova
10/2004 – 7/2005 (10 Monate)
Luft- und Raumfahrtindustrie
Tätigkeitszeitraum

10/2004 – 7/2005

Tätigkeitsbeschreibung

Analysis of the NH90 NAHEMA SMS Release Controls and Safety Interlocks FPGAs to verify engineering requirements and specifications.
- Writing the documentation for the existing VHDL code
- Coding a Test Bench to cover/simulate the FPGA requirements.
- Fixing bugs
Boards modification to be compliant to the new client requirements (NH90 NORDIC)
- Specification of the new requirements
- Coding and integrating the new VHDL functionalities.
- Coding a Test Bench to cover/simulate the FPGA
- Re-design of the test rig (schematic, VHDL and control software) to allow testing the old and new boards and to add some new capabilities (scripting language)
- Writing scripts to test all the electronic on board.
- Documenting all the stages of the process in accordance with company standards and methodologies ( DAL B).
- Design and implementation of a StingRay torpedo and a Marte MK2 Anti Ship
Missile simulators.
- VHDL code
- C++ code to create an interactive windows interface

Eingesetzte Qualifikationen

Hardware Entwicklung, VHDL (VHSIC Hardware Description Language)


Hardware Engineer
Selex Communications (former Marconi), Genova
10/2004 – 7/2005 (10 Monate)
Luft- und Raumfahrtindustrie
Tätigkeitszeitraum

10/2004 – 7/2005

Tätigkeitsbeschreibung

Analysis of the NH90 NAHEMA SMS Release Controls and Safety Interlocks FPGAs to verify engineering requirements and specifications.
- Writing the documentation for the existing VHDL code
- Coding a Test Bench to cover/simulate the FPGA requirements.
- Fixing bugs
Boards modification to be compliant to the new client requirements (NH90 NORDIC)
- Specification of the new requirements
- Coding and integrating the new VHDL functionalities.
- Coding a Test Bench to cover/simulate the FPGA
- Re-design of the test rig (schematic, VHDL and control software) to allow testing the old and new boards and to add some new capabilities (scripting language)
- Writing scripts to test all the electronic on board.
- Documenting all the stages of the process in accordance with company standards and methodologies ( DAL B).
- Design and implementation of a StingRay torpedo and a Marte MK2 Anti Ship
Missile simulators.
- VHDL code
- C++ code to create an interactive windows interface

Eingesetzte Qualifikationen

Field Programmable Gate Array (FPGA), Hardware Entwicklung, VHDL (VHSIC Hardware Description Language), Luft- und Raumfahrttechnik (allg.)


Hardware Engineer
Teleavio SRL, Genova
6/2002 – 10/2004 (2 Jahre, 5 Monate)
Luft- und Raumfahrtindustrie
Tätigkeitszeitraum

6/2002 – 10/2004

Tätigkeitsbeschreibung

Aermacchi M-346 Project:
Re-Design of the Central Processing Unit (CPU) and Input Output Controller (IOC) boards for
the M346 Aircraft's Flight Control Computer (FCC).
- VHDL coding of the safety critical (DAL A) FPGAs
- Test-Bench creation and simulation using ModelSim to verify the design.
- Static timing analysis.
- Schematic design.
- Design of automatic on board tests using assembly and C for the PowerPC603 microprocessor (CPU board) and the TI C6701 Digital Signal Processor (IOC board) to ease prototype debugging and industrialization process. Tests include: 1553 avionics bus, Arinc429, Cross Channel Data Link, Interrupt controller, timers, memories and any other on board device.
- Help on the software-hardware integration stages, where a good knowledge of the
existing hardware is required along with the capability of understanding the
software design and requirements.
- Documenting all the stages of the process in accordance with company standards and methodologies.

Eingesetzte Qualifikationen

Field Programmable Gate Array (FPGA), Hardware Entwicklung, VHDL (VHSIC Hardware Description Language), Luft- und Raumfahrttechnik (allg.)


Ausbildung

Master of Science, Computer Science Engineering
(Master of Science, Computer Science Engineering)
Jahr: 2001
Ort: Zaragoza, Spain

Qualifikationen

Master of Science, Computer Science Engineering

Über mich

Freelance Hardware Engineer specializing in aerospace technologies (all safety Levels) with a very good safety and software understanding.

Certification Support:
Successful track of presentations to EASA (ranging from SOI#1 to SOI#4) that resulted in the successful certification of three different projects (including DALs A and C).

Persönliche Daten

Sprache
  • Spanisch (Muttersprache)
  • Englisch (Fließend)
  • Deutsch (Gut)
  • Italienisch (Fließend)
  • Französisch (Fließend)
Reisebereitschaft
auf Anfrage
Arbeitserlaubnis
  • Europäische Union
  • Schweiz
Home-Office
unbedingt
Profilaufrufe
313
Alter
43
Berufserfahrung
19 Jahre und 5 Monate (seit 09/2001)

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