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FPGA Development Engineer

offline
  • auf Anfrage
  • 82178 Puchheim, Oberbayern
  • auf Anfrage
  • ar  |  en  |  de
  • 26.01.2022

Kurzvorstellung

I am a dedicated hard worker communication and hardware engineer highly interested in hardware design and simulation. I am experienced in advanced digital communication systems and implementing protocols on hardware and applying massive simulations.

Qualifikationen

  • Bash (Shell)
  • C#
  • C++
  • Emacs
  • Firmware
  • Git
  • Linux (Kernel)
  • make (Software)
  • MATLAB / Simulink
  • Python
  • Quartus (Altera)
  • TCL/TK
  • VHDL (VHSIC Hardware Description Language)
  • Vivado (Xilinx)

Projekt‐ & Berufserfahrung

FPGA Development Consultant
Qualcomm, Munich
8/2021 – offen (2 Jahre, 9 Monate)
Telekommunikation
Tätigkeitszeitraum

8/2021 – offen

Tätigkeitsbeschreibung

Building a graphical user interface between the PC and the FPGA as remote access instead of hardware managing platform using C#.

Eingesetzte Qualifikationen

Bash (Shell), C#, TCL/TK, VHDL (VHSIC Hardware Description Language)

FPGA Development Engineer (Festanstellung)
ARECS GmbH, Puchheim
9/2017 – 7/2021 (3 Jahre, 11 Monate)
Telekommunikation
Tätigkeitszeitraum

9/2017 – 7/2021

Tätigkeitsbeschreibung

I worked on implementing a transceiver using customized protocol. Research was held to find out the best method in capturing the received signal. My work was focused on simulating different techniques using MATLAB referring to benchmarked results. After choosing the appropriate technique, I implemented it on FPGA using VHDL taking into consideration timing constraints. Every code was placed in a testing environment where every update stimulate this environment to produce the success or failure of the
architecture. The hardware part was also attached with a software part where I established the MAC layer in C language.
Another project I worked on is the hardware module of an interferometer. This
project was proposed by well-known firm in lenses domain ZEISS. The architecture of this project was demonstrated in VHDL, and a detailed report covering testing results, constraints, and register mapping was submitted upon finalizing the whole model. The final project that I worked on in my current firm is Local Interconnect Network (LIN) core slave deployed on FPGA.

Eingesetzte Qualifikationen

Firmware, MATLAB / Simulink, VHDL (VHSIC Hardware Description Language), Vivado (Xilinx)

Ausbildung

Hardware and Communication Engineering
Masters of Engineering
2021
American University of Beirut
Computer and Communication Engineering
Bachelor of Engineering

American University of Beirut

Über mich

Expert in documenting and presenting results through MS office

Weitere Kenntnisse

MS office expert

Persönliche Daten

Sprache
  • Arabisch (Muttersprache)
  • Englisch (Fließend)
  • Deutsch (Grundkenntnisse)
Reisebereitschaft
auf Anfrage
Arbeitserlaubnis
  • Europäische Union
Profilaufrufe
594
Alter
28
Berufserfahrung
6 Jahre und 10 Monate (seit 06/2017)

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