Analog Layout Expert

10/2017 – 1/2020

Floorplan, power plan, Manual ECOs, cell Placement and Routing optimization on timing or RV critical nets and area in different processes.
•IP, LVS, EM,DRC, DFM fixes for different process nodes

Lead & Management Experience:

• Helped the organization to build a quality team, training team to meet customer standards
• Good exposure to cross site and cross geo work styles
• Proven record of managing and executing multiple complex projects simultaneously in tight timeline.
• Proven record of managing a large team and maintaining on time project delivery consistently with quality.
• Build, train & mentor the team to take up next level
• Technical assistance & Layout review for the team
• Performance management and assessment of engineers
• Received ‘Best Project Manager – VLSI’ Award from UST Global, Malaysia.

Microsemi (allg.)

9/2016 – 9/2017

Waferspace is a service based company. From wafer space worked for TI. In Worked on toccoa_tx in 65nm process for TI. Helping team in technical details and execution.

Microsemi (allg.)

8/2011 – 6/2016

• Handling layout from floorplan stage for the new blocks & implementing ecos based on the need for existing blocks.
• HV fixes, RV fixes and ensuring timing criteria is met.
• Scarlet Extraction, Other Layout verifications, Density Fixes & Layout review.
• DDR, PLL, LGCIO, FIVR are handled by different teams from client side and as supplier team handled everything together and ensured quality delivery for all within designated milestone closure period.
• Assessing the Scope of given tasks & technical discussions with cross site team.
• Training new members in team on methodology, tools and project specs.
• Assigning tasks to team based on their technical strengths.
• Technical support to team and ensuring on time quality delivery.
• Helping client to meet critical milestone closure timelines through proper execution planning.
TigerLake (TGL): Digital

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