ASIC / Chip / Hardware Entwickler

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I am a ASIC / Chip Design Engineer with more than 12 Years of work experience. I am into Analog Mixed Signal Design/Simulation/Layout/Full-chip Parasitic Extraction/Backend Verification. Also have exp. in Mixed-Signal Verification and Digital Design

Ich biete

Technik, Ingenieurwesen
  • Elektrotechnik
  • Elektronik

Projekt‐ & Berufserfahrung

Cisco GmbH / Coreoptics GmbH, Nürnberg
12/2011 – 7/2012 (8 Monate)
Elektrotechnik - ASIC / Chip Entwicklung

12/2011 – 7/2012


- Project consulting for next generation CISCO routers topping 60G/Sec

- Schematic changes of high level blocks using Cadence Virtuoso + Monte Carlo, Process Corner and ENOB simulations of ADC – Using ADEL

- Full custom Analog Layout of DAC blocks in TSMC 28nm technology. Layout Verification DRC, LVS, EMC, SXRC and Density Verification checks


Masters of Science in Electrical Engineering / System Design and Technology
Juli 2002

Bachelors of Engineering, Electronics and Communication Engineering
April 1998


- Elektrotechnik
- Hardware-Entwicklung
- ASIC Entwicklung
- Full Custom Layout
- Timing and Finctionality Verification
- Full-chip Parasitic Extraction and Simulation
- Chip Back-end Verification
- Analog Mixed Signal Verification
- Analog and Digital IP Creation

Über mich

Profile summary / Objective

An extremely motivated and target oriented IC Design Engineer. My target is to work in a responsible role in Analog Mixed Signal Design bringing together various inter disciplinary teams together. Solving problems, through my expertise developed over the years, improving the business position of the company that I work for. I have over 12 years of work experience in the field of Microelectronics and a Masters Degree holder


Analog Design - High Speed ADC, DAC, Analog Transistor Level Design, Automotive Blocks Know how – LIN, HSS, ADC, Temperature Sensors etc.
Full chip Parasitic Extraction and Re-simulation, Process corner and Monte Carlo simulations, Sub-Micron Effect simulations in Design
Full custom Analog Layout & Layout verification in 28nm technologies (DRC, LVS, SXRC, EMC, Density checks etc.)

Digital Design – Functional, Synthesis, Timing (Verilog, VHDL model generation), Process Corner Simulation, Critical path timing Analysis, Digital Transistor Library, Design and Simulation (Standard, High–Speed, Low–Power, Low–Noise), Automatic Place and Route (APR)

Verification - Digital, Analog and Mixed Signal Verification – Automotive chips; Experience in verification of Analog Test Bus (ATB) and back-end Verification of Intel Chip-sets

Foundry Process

1.0µ to 0.35µ Analog Mixed Signal Process targeting Automotive Applications
110nm to 65nm Digital Memory Technologies; 65nm Processor chipset; 28nm targeting High Speed Communication


Cadence - Schematic Entry, ADE–L, Virtuoso Layout Editor, Verification Assura
Synopsys – HSPICE, NanoSim, PrimeTime, Star Extract, Synthesis
Mentor Graphics – DA–IC, IC Station, Calibre nmDRC, LVS
Company Specific tools - Intel Internal Analog Simulator, XFAB Library Characterizer, Infineon verification Tools
Other Languages / Tools – Altera FPGA, Verilog, AMS, VHDL, Matlab, Ample, C, Perl, MS Office, Linux/Sun OS

Persönliche Daten

  • Tamil (Muttersprache)
  • Deutsch (Fließend)
  • Englisch (Muttersprache)
18 Jahre und 1 Monat (seit 11/2000)
3 Jahre


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