Harsha_curriculum_vitae

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65€/Stunde
70372 Stuttgart
04.02.2014

Kurzvorstellung

Dear Sir/Madam,

I have a Master’s degree in VLSI Design and Embedded Systems.
I have 6+yrs of experience in ASIC/FPGA and mastered all phase of design, verification and validation.

Ich biete

Technik, Ingenieurwesen
  • Funktechnik
  • Elektrotechnik
  • Elektronik
  • Nachrichtentechnik

Projekt‐ & Berufserfahrung

Digital Design Engineer
Dialog Semiconductor GmBH, Stuttgart
4/2013 – 9/2013 (6 Monate)
High-Tech- und Elektroindustrie
Tätigkeitszeitraum

4/2013 – 9/2013

Tätigkeitsbeschreibung

Design and Verification of Button Control, GPIO and Single/Two finger reset.


Technical Consultatnt
Alcatel Lucent Bell Labs,, Stuttgart
8/2012 – 1/2013 (6 Monate)
Telekommunikation
Tätigkeitszeitraum

8/2012 – 1/2013

Tätigkeitsbeschreibung

Design of Analog Control Module : FPGA, VHDL , Test and Validation on Board.


Technical Consultant
Samsung Electronics, Suwon, Seoul
12/2009 – 4/2012 (2 Jahre, 5 Monate)
Telekommunikation
Tätigkeitszeitraum

12/2009 – 4/2012

Tätigkeitsbeschreibung

Design of RRH module for GSM network
Involved in development of upload and download transmission path for RRH system which involved mapping of GSM frame to CPRI line rate of 2.5GHz and mapping the data to different RF paths.

Partial Reconfiguration of FPGA
Partial reconfiguration is a design process that allows a limited, predefined portion of an FPGA to be partitioned and reconfigured while the remainder of the device continues to operate.

Verification of CPRI for 2.5GHz and 4.5Ghz
Involved in implementation of CPRI on Virtex 6 device and test its reliability with cascaded architecture having minimum round-trip delay.

Implementation of ADC and DAC interface for High-speed DDR data
Configuring ADC (ADS62P49) and DAC (DAC5688) to meet the new requirements of high speed DDR interface. Calibrating the FPGA using ODDR, IDDR, IDELAYCTRL and IODELAYE1 primitive elements to meet the requirement and have a reliable eye opening for efficiency.


Senior Software Engineer
L & T Infotech, Bangalore
8/2006 – 7/2012 (6 Jahre)
Telekommunikation
Tätigkeitszeitraum

8/2006 – 7/2012

Tätigkeitsbeschreibung

Design of WiMac physical layer modules on FPGA.


Ausbildung

VLSI Design and Embedded System
(Master of technology)
Jahr: 2007
Ort: Mysore, India

Qualifikationen

VHDL, Verilog, System Verilog.
Python and Shell Scripts.
FPGA - XILINX and ALTERA.
ISE, QUARTUS, PlahAhead, MATLAB.

Über mich

I am self-motivated and always willing to learn new methods that lead to performing better in different spheres of my work.

A large part of my career up to now has been focused on studying complex algorithms of complete systems and rendering them in hardware.

Specialties
VHDL, Verilog and FPGA.

Persönliche Daten

Sprache
  • Deutsch (Grundkenntnisse)
  • Englisch (Fließend)
  • Koreanisch (Grundkenntnisse)
  • Hindi (Muttersprache)
Reisebereitschaft
Weltweit
Arbeitserlaubnis
  • Europäische Union
Profilaufrufe
696
Alter
35
Berufserfahrung
12 Jahre und 3 Monate (seit 08/2006)

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