Kurzvorstellung
Development of embedded processor based system-on-chip designs for handheld, networ
Ich biete
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Elektrotechnik
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Elektronik
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Ingenieurwissenschaft
Projekt‐ & Berufserfahrung
Luft- und Raumfahrtindustrie
10/2015 – 9/2017
Tätigkeitsbeschreibung
VHDL design of satellite X-ray camera sensor control ASIC.
VHDL design of instrument control unit (Space wire Router).
VHDL (VHSIC Hardware Description Language)
Infineon Technologies, Villach
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Automobilindustrie
3/2011 – 2/2014
TätigkeitsbeschreibungDigital Mixed Signal ASIC design of automotive smart power switches.
Eingesetzte QualifikationenVHDL (VHSIC Hardware Description Language)
Konsumgüterindustrie
10/2010 – 12/2010
TätigkeitsbeschreibungASIC design of NFC frontend.
Eingesetzte QualifikationenVerilog HDL
Luft- und Raumfahrtindustrie
6/2010 – 9/2010
Tätigkeitsbeschreibung
ISSR Satellite downlink controller (VHDL)
Mass memory-transmitter data path BIST (VHDL, Verilog),
Sign-off verification (TCL, SystemVerilog)
TCL/TK, Controlling
High-Tech- und Elektroindustrie
4/2009 – 5/2010
Tätigkeitsbeschreibung
Physical design (constraining-80 clocks, synthesis 90nm,
400 MHz, layout guidance)
Microsoft Access, TCL/TK
High-Tech- und Elektroindustrie
5/2005 – 3/2009
Tätigkeitsbeschreibung
System-on-chip module development (RTL design,
DFT, verification, FPGA prototyping) (3 ASICs)
Physical design (constraining-80 clocks, synthesis 90nm,
500 MHz, layout guidance) (3 ASICs)
Project management (planning, customer support) (2 ASICs)
Design flow development (Perl, TCL, SQL)
SQL, Perl, TCL/TK, IT-Support (allg.), Technisches Projektmanagement, Projektmanagement
Konsumgüterindustrie
7/2002 – 4/2005
TätigkeitsbeschreibungMixed Signal Design of semicustom RAM, Ring oscillator, charge pump.
Eingesetzte QualifikationenVerilog HDL
Konsumgüterindustrie
4/2000 – 12/2001
Tätigkeitsbeschreibung
SOC design and verification.
Design of ADC digital control.
Verilog HDL
High-Tech- und Elektroindustrie
6/1999 – 12/1999
Tätigkeitsbeschreibung
FPGA validation of HC12 µC SoC
(top-level design, FPGA synthesis)
Prototype board of HC12 µC (5 FPGA 240-pin)
(Board schematics, layout)
Schnittstellenentwicklung, Elektrotechnik, Elektronik
High-Tech- und Elektroindustrie
10/1997 – 3/1998
TätigkeitsbeschreibungUniversal scalable, programmable parallel-interface (specification, RTL design, synthesis)
Eingesetzte QualifikationenKonzeption (IT)
Ausbildung
(2.7)
Ort: FH München
(3.2)
Ort: FH Nürnberg
Qualifikationen
Development of embedded processor based system-on-chip designs for handheld, networking, automotive and space applications.
High speed SoC integration (400 MHz) for networking applications.
Development of handheld portable low power TFT display controller.
Development of memory controller including asynchronous arbiters.
Development of Power Management ICs ( voltage domain, power domains, CDC )
Experience with asynchronous logic design with no clocks.
Development of built-in self-calibration and self-testing methods.
Design support for post-silicon validation and live time problem solving.
Experience in UPF based SoC, simulation, synthesis (power domains, isolation cells and power switches)
Expertise on developing complex timing constraints for multi-mode STA and P&R.
Assertion based formal verification (Cadence IFV, Spyglass).
Experience with FPGA development and prototyping (Altera, XILINX).
Basic knowledge of RF transceiver development (ISO 14443).
Basic knowledge of digital signal processing.
Advanced RTL coding using SystemVerilog, VHDL or Verilog.
Configuration management (ClearCase).
Expertise on creating design flow, executable specification (Perl, TCL, SQL, Skill).
Project management (task assignment, schedule and communication).
Low-level design know-how, schematics and design at gate-level.
Basic working knowledge of transistor level analogue design including layout.
Semicustom design of control logic for low power SRAM in schematics.
Design of capacitive/inductive 4-stage boost DC/DC converter.
Mixed-signal simulation and modeling using VerilogA and VHDL-AMS
Familiar with Cadence AMS design environment
(Virtuoso, Encounter), Synopsys ICC and Mentor Calibre.
Familiar with Mathematica, Matlab/Simulink.
Hands-on experience on microwave engineering including design
of matching networks, low noise amplifiers and filters using ADS.
Generation of new ideas and solutions.
Persönliche Daten
- Deutsch (Muttersprache)
- Englisch (Fließend)
- Spanisch (Gut)
- Europäische Union
- Schweiz
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