Digital Mixed-Signal Design Engineer

Profil Foto
Verfügbarkeit einsehen
Weltweit
de  |  en  |  es
auf Anfrage
85359 Freising
08.12.2018

Kurzvorstellung

All steps of IC design from concept engineering through architecture development, specification, design, verification, physical design, to production ramp up support.
Development of embedded processor based system-on-chip designs for handheld, networ

Ich biete

Technik, Ingenieurwesen
  • Elektrotechnik
  • Elektronik
Forschung, Wissenschaft, Bildung
  • Ingenieurwissenschaft

Projekt‐ & Berufserfahrung

Senior Design Engineer
EADS Astrium, München
6/2010 – 9/2010 (4 Monate)
Luft- und Raumfahrtindustrie
Tätigkeitszeitraum

6/2010 – 9/2010

Tätigkeitsbeschreibung

ISSR Satellite downlink controller (VHDL)
Mass memory-transmitter data path BIST (VHDL, Verilog),
Sign-off verification (TCL, SystemVerilog)

Eingesetzte Qualifikationen

TCL/TK, Controlling


Senior ASIC Design Engineer
Siemens, Karlsruhe
4/2009 – 5/2010 (1 Jahr, 2 Monate)
High-Tech- und Elektroindustrie
Tätigkeitszeitraum

4/2009 – 5/2010

Tätigkeitsbeschreibung

Physical design (constraining-80 clocks, synthesis 90nm,
400 MHz, layout guidance)

Eingesetzte Qualifikationen

Microsoft Access, TCL/TK


Senior ASIC Design Engineer
Siemens, Amberg
5/2005 – 3/2009 (3 Jahre, 11 Monate)
High-Tech- und Elektroindustrie
Tätigkeitszeitraum

5/2005 – 3/2009

Tätigkeitsbeschreibung

System-on-chip module development (RTL design,
DFT, verification, FPGA prototyping) (3 ASICs)
Physical design (constraining-80 clocks, synthesis 90nm,
500 MHz, layout guidance) (3 ASICs)
Project management (planning, customer support) (2 ASICs)
Design flow development (Perl, TCL, SQL)

Eingesetzte Qualifikationen

SQL, Perl, TCL/TK, IT-Support (allg.), Technisches Projektmanagement, Projektmanagement


Presilicon Emulation
Motorola - Freescale, München
6/1999 – 12/1999 (7 Monate)
High-Tech- und Elektroindustrie
Tätigkeitszeitraum

6/1999 – 12/1999

Tätigkeitsbeschreibung

FPGA validation of HC12 µC SoC
(top-level design, FPGA synthesis)
Prototype board of HC12 µC (5 FPGA 240-pin)
(Board schematics, layout)

Eingesetzte Qualifikationen

Schnittstellenentwicklung, Elektrotechnik, Elektronik


ASIC Designer
Fraunhofer ISS, Erlangen
10/1997 – 3/1998 (6 Monate)
High-Tech- und Elektroindustrie
Tätigkeitszeitraum

10/1997 – 3/1998

Tätigkeitsbeschreibung

Universal scalable, programmable parallel-interface (specification, RTL design, synthesis)

Eingesetzte Qualifikationen

Konzeption (IT)


Ausbildung

Elektrotechnik - Hochfrequenztechnik
(2.7)
Jahr: 2007
Ort: FH München

Elektrotechnik - Mikroelektronik
(3.2)
Jahr: 2000
Ort: FH Nürnberg

Qualifikationen

All steps of IC design from concept engineering through architecture development, specification, design, verification, physical design, to production ramp up support.
Development of embedded processor based system-on-chip designs for handheld, networking, automotive and space applications.
High speed SoC integration (400 MHz) for networking applications.
Development of handheld portable low power TFT display controller.
Development of memory controller including asynchronous arbiters.
Development of Power Management ICs ( voltage domain, power domains, CDC )
Experience with asynchronous logic design with no clocks.
Development of built-in self-calibration and self-testing methods.
Design support for post-silicon validation and live time problem solving.
Experience in UPF based SoC, simulation, synthesis (power domains, isolation cells and power switches)
Expertise on developing complex timing constraints for multi-mode STA and P&R.
Assertion based formal verification (Cadence IFV, Spyglass).
Experience with FPGA development and prototyping (Altera, XILINX).
Basic knowledge of RF transceiver development (ISO 14443).
Basic knowledge of digital signal processing.
Advanced RTL coding using SystemVerilog, VHDL or Verilog.
Configuration management (ClearCase).
Expertise on creating design flow, executable specification (Perl, TCL, SQL, Skill).
Project management (task assignment, schedule and communication).
Low-level design know-how, schematics and design at gate-level.
Basic working knowledge of transistor level analogue design including layout.
Semicustom design of control logic for low power SRAM in schematics.
Design of capacitive/inductive 4-stage boost DC/DC converter.
Mixed-signal simulation and modeling using VerilogA and VHDL-AMS
Familiar with Cadence AMS design environment
(Virtuoso, Encounter), Synopsys ICC and Mentor Calibre.
Familiar with Mathematica, Matlab/Simulink.
Hands-on experience on microwave engineering including design
of matching networks, low noise amplifiers and filters using ADS.
Generation of new ideas and solutions.

Persönliche Daten

Sprache
  • Deutsch (Muttersprache)
  • Englisch (Fließend)
  • Spanisch (Gut)
Reisebereitschaft
Weltweit
Arbeitserlaubnis
  • Europäische Union
  • Schweiz
Profilaufrufe
375
Alter
49
Berufserfahrung
18 Jahre und 8 Monate (seit 04/2000)
Projektleitung
4 Jahre

Kontaktdaten

Nur registrierte PREMIUM-Mitglieder von freelance.de können Kontaktdaten einsehen.

Jetzt Mitglied werden »