freiberufler Senior Digital Mixed-Signal Design Engineer auf freelance.de

Senior Digital Mixed-Signal Design Engineer

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  • 85356 Freising
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  • 25.02.2021

Kurzvorstellung

All steps of IC design from concept engineering through architecture development, specification, design, verification, physical design, to production ramp up support.
Development of embedded processor based system-on-chip designs for handheld.

Ich biete

  • Humanmedizin
  • Ingenieurwissenschaft
  • Psychologie (allg.)

Projekt‐ & Berufserfahrung

ASIC Design Engineer (Festanstellung)
Max Planck Institute, Garching
10/2015 – 9/2017 (2 Jahre)
Luft- und Raumfahrtindustrie
Tätigkeitszeitraum

10/2015 – 9/2017

Tätigkeitsbeschreibung

Full custom layout of Flip-Flop-RAM (Virtuoso)
Development of satellite camera source and gate-driver control (driving scheme) (VHDL, Assembly)
Development of SpaceWire Transceiver based on own RISC processor (VHDL, Assembly)
Development of 64-bit RISC processor (VHDL, synthesis 350 nm)
Transfer of Merlin satellite X-ray camera source read-out and gate driver ASIC to own library (top-level simulation, buffer balancing, noise) (Primetime, ModelSim)
Development of a radiation hardened library (Synopsys, Nanotime, Conformal)

Eingesetzte Qualifikationen

VHDL (VHSIC Hardware Description Language)

Digital/Mixed-Signal Design Engineer (Festanstellung)
Infineon Technologies ATV BP, Villach
3/2011 – 2/2014 (3 Jahre)
Semiconductors
Tätigkeitszeitraum

3/2011 – 2/2014

Tätigkeitsbeschreibung

Development of a bus-system for smart power switches (VHDL)
Development of Chip-on-package ASIC for temperature measurement and estimation of FINFET (top-level, digital control, layout of Pad-ring, PnR) (VHDL, Questa ADMS, UVM, UPF, Synopsys DC, ICC, Primetime, Virtuoso)
Top-level fault simulation of mixed-signal ASIC (VeriFault)
Development of automotive 24-channel master-CPU for smart power switches (VHDL)

Eingesetzte Qualifikationen

VHDL (VHSIC Hardware Description Language)

Digital Mixed signal design engineer (Festanstellung)
NXP, Gratkorn
10/2010 – 12/2010 (3 Monate)
Semiconductors
Tätigkeitszeitraum

10/2010 – 12/2010

Tätigkeitsbeschreibung

Concept development RF-transceivet, asynchronous FIFO for NFC frontend

Eingesetzte Qualifikationen

Verilog HDL

Senior Design Engineer
EADS Astrium, München
6/2010 – 9/2010 (4 Monate)
Luft- und Raumfahrtindustrie
Tätigkeitszeitraum

6/2010 – 9/2010

Tätigkeitsbeschreibung

Design ISSR satellite CCSDS packet receiver (SystemVerilog)
Design ISSR satellite mass memory read out controller (VHDL)

Eingesetzte Qualifikationen

VHDL (VHSIC Hardware Description Language)

Senior ASIC Design Engineer
Siemens, Amberg/Karlsruhe
5/2005 – 5/2010 (5 Jahre, 1 Monat)
Semiconductors
Tätigkeitszeitraum

5/2005 – 5/2010

Tätigkeitsbeschreibung

Physical design (constraining-80 clocks, synthesis 90nm,
500 MHz, layout guidance) (3 ASICs)
System-on-chip module development (RTL design,
DFT, verification, FPGA prototyping) (3 ASICs)
Project management (planning, customer support) (2 ASICs)
Design flow development (Perl, TCL, SQL)

Eingesetzte Qualifikationen

Perl, SQL, TCL/TK, Technisches Projektmanagement, VHDL (VHSIC Hardware Description Language)

Development Engineer (Festanstellung)
Philips Semiconductors (NXP), Böblingen
7/2002 – 4/2005 (2 Jahre, 10 Monate)
Semiconductors
Tätigkeitszeitraum

7/2002 – 4/2005

Tätigkeitsbeschreibung

Capacitive, inductive 4-stage boost DC/DC converter (VHDL)
Development of RAM top-level (semicustom design, layout) (2 ASICs)
Design asynchronous self-clocking serializer/deserializer (Innovation) (specification, gate-level design, layout) (2 ASICs)
Design low power SRAM controller (2 ASICs)
Asynchronous burst mode RAM arbiter (Innovation) (specification, gate-level design) (3 ASICs)
Redesign oscillator (transistor-level analog design)
Design flow development (Skill)

Eingesetzte Qualifikationen

Verilog HDL

IC Design Engineer (Festanstellung)
National Semiconductors (TI), Fürstenfeldbruck
4/2000 – 12/2001 (1 Jahr, 9 Monate)
Semiconductors
Tätigkeitszeitraum

4/2000 – 12/2001

Tätigkeitsbeschreibung

Design on-chip self-calibration module for GHz folding ADC (innovation) (specification, Verilog, synthesis 180nm)
SoC verification (multifunctional timer, image sensor, airbag controller) (Verilog, Assembly, VCS) (3 ASICs)
USB 1.1 module design, verification and DFT (Verilog)
Design flow development (TCL, Perl)

Eingesetzte Qualifikationen

Verilog HDL

Presilicon Emulation
Motorola (Freescale) (NXP) MCU Design Center, München
6/1999 – 12/1999 (7 Monate)
Semiconductors
Tätigkeitszeitraum

6/1999 – 12/1999

Tätigkeitsbeschreibung

FPGA validation of HC12 µC SoC
(top-level design, FPGA synthesis)
Prototype board of HC12 µC (5 FPGA 240-pin)
(PCB schematics, layout)
Design flow development (Perl)

Eingesetzte Qualifikationen

Elektronik, Schnittstellenentwicklung

ASIC Designer
Fraunhofer ISS ASIC Design Center, Erlangen
10/1997 – 3/1998 (6 Monate)
Semiconductors
Tätigkeitszeitraum

10/1997 – 3/1998

Tätigkeitsbeschreibung

Universal scalable, programmable parallel-interface (specification, RTL development, synthesis)

Eingesetzte Qualifikationen

VHDL (VHSIC Hardware Description Language)

Ausbildung

NLP Master
(Ausbildung)
Jahr: 2014
Ort: Inntal
Elektrotechnik - Hochfrequenztechnik
(2.6)
Jahr: 2008
Ort: FH München
Tiefen und Gestalt Pädagoge
(Ausbildung)
Jahr: 2006
Ort: München
Elektrotechnik - Mikroelektronik
(3.2)
Jahr: 2000
Ort: FH Nürnberg

Qualifikationen

All steps of IC design from concept engineering through architecture development, specification, design, verification, physical design, to production ramp up support.
Experience with development of RISC processors (Chameleon, COP32, HC12, SIMATIC, Infineon).
Development of SoCs for automation, networking and automotive applications.
Development of handheld portable low power TFT display controller.
Development of memory controller including asynchronous arbiters.
Experience with asynchronous logic design with no clocks.
Development of built-in self-calibration and self-testing circuitry.
Experience with development of automotive smart HS and LS driver.
Schematics and gate-level design know-how.
Basic working knowledge of transistor level analogue design including layout.
Semicustom design of control logic for low power SRAM in schematics.
Mixed-signal simulation and behavioral modeling (VerilogA).
Design of capacitive/inductive 4-stage boost DC/DC converter.
Familiar with Cadence Design Framework (Virtuoso, Calibre, StarRC).
RTL coding (SystemVerilog, VHDL, Verilog).
Experience with setup of UVM environment, generation of registers (SystemVerilog).
High speed SoC integration (400 MHz) for networking applications.
Experience with UPF based SoC simulation, synthesis (power domains, CDC).
Expertise on developing complex timing constraints for multi-mode STA and P&R.
Experience with digital and analog layout (ICC, SiliconEnsemble, Virtuoso).
Experience with Library development (timing extraction, equivalence checking) (Nanotime, Conformal).
Formal RTL and gate-level sign-off checks using (Incisive, Conformal, SpyGlass).
Experience with FPGA prototyping (XILINX).
Configuration management (ClearCase).
Expertise on creating design flow (Perl, TCL, Skill, MS Access).
Support for post-silicon validation and live time problem solving.
Project management (task assignment, schedule using MS Project).
Generation of new ideas and solutions.
English - fluent (spoken and written)
Spanish - good working knowledge

Persönliche Daten

Sprache
  • Deutsch (Muttersprache)
  • Englisch (Fließend)
  • Spanisch (Gut)
Reisebereitschaft
Weltweit
Arbeitserlaubnis
  • Europäische Union
  • Schweiz
Profilaufrufe
1375
Alter
51
Berufserfahrung
20 Jahre und 11 Monate (seit 04/2000)
Projektleitung
4 Jahre

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