FPGA | Software & Embedded-SW | Yocto-Petalinux | Data Analysis | Verification & Validation

4/2024 – 3/2026

■ Introduction of a new Data-Path concept to improve throughput, integrity & post-processing

■ Introduction & Implementation of a new Fly-System configuration & monitoring concept

■ Implementation of various IPs and AXI busses (Lite & Stream) for PS-to-PL and IP-to-IP communication

■ Implementation of various configuration & data interfaces: Laser, SPADs via TDC, Encoder-EnDAT2.2, FSM, SPI, I2C, SSH, DDR3

■ Implementation of an artificial Photon/Return generator for Pre-Flight-Ground-Tests and various characterizations (TDC & Data-Rate)

■ Implementation of timing engine for system-wide synchronization with the Laser-Fire pulse.

■ Implementation of a Smart-Filter to dynamically adapt the Range-Gate of Returns to the PCIe bandwidth, without losing the ground

■ Implementation of a dynamic AGL estimator, based on average TOF (Time-Of-Fly) from all TDC-FPGAs

■ Implementation & packeting of data from various sources (PPS, Laser-Pulse, Histogram, Returns, Encoder, FSM) and streaming over multiple high-speed layers: Aurora at 5Gbs & PCIe at 4GBs (Gen3x4)

■ Yocto/Petalinux setup & implementation of various real-time apps to interact with PS

■ Specification & Implementation of a new shell script to configure the Fly-System via SSH

■ Specification & Implementation of a new shell script to dynamically monitor the system during the flight via SSH

■ Flight-Parameter definition & Flight-Data analysis

■ Operated as R&D expert in the plan to monitor & debug the system during the flight

■ Highly contributed to raise the project from a nearby cancellation to Success

■ Successful imaging with LiDAR & MFC data on all terrains (City, Land, Green-Fields, Mountains, Water), at 2500m..4500m flight-height, at various photon sensitivity levels and at high-speed

Full project description and job references can be found as attachments in the "Persönliches Portfolio" section

Bash Shell, Confluence, Docker, Embedded Linux, Ethernet, FPGA, Git, Jira, Json, Laser-systeme, Lua Scripting, Programmierer C, C++, Python, SSH (Secure Shell), Ubuntu, Virtualbox, Vivado (Xilinx), Xilinx (allg.)

8/2023 – 10/2023

FPGA firmware development for the automation of control cabinets

The regulation and query of the IOs connected to the FPGA is controlled by an ARM-based 32-bit MCU

After a meticulous system requirements analysis, the SPI bus has been selected as interface between MCU and FPGA, where the MCU acts as master and the FPGA as slave

■ Review of the FPGA circuit with regard to configuration and SPI interface to the MCU: pin assignment, voltage, termination, additional or missing IOs, etc.

■ Important findings and crucial design change suggestions to minimize: Cross-talks, propagation delays, setup/hod-time errors, etc.

■ Specification of the communication protocol between MCU and FPGA, and the memory mapping inside FPGA

■ Integration of a new method for data integrity check on SPI via CRC-16, without violating the SPI protocol standard

■ Implementation of a generic SPI slave in the FPGA, with corresponding memory connection to internal register banks

■ Implementation of a generic SPI master in the FPGA, which acts as MCU in simulation mode

■ The SPI bus is generic and configurable as Standard, Dual or Quad SPI

■ Implementation of a solid simulation infrastructure, with corresponding description and simulation file with various test cases

■ Simulation of all communication protocols between MCU and FPGA: Standard/Dual/Quad mode, data integrity check, etc.

■ Crash course for internal employees: FPGA, VHDL, Xilinx-Vivado, modern simulation methods, critical paths in FPGA design, critical reports, timing closure

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Einzelne Projektbeschreibungen finden Sie als Anhang im Bereich "Persönliches Portfolio"
Individual project descriptions can be found as attachments in the "Persönliches Portfolio" section

Bash Shell, Elektronische Schaltungstechnik, FPGA, Hardwarebeschreibungssprache, Picmicro, Schulung / Coaching (allg.), STM32, Systems Simulation, Technische Dokumentation, Tool Command Language, Vivado (Xilinx), Xilinx (allg.)

6/2015 – 2/2023

■ Department: PDPC (Philips Digital Photon Counting)

■ Business: CT/AMI (Computing Tomography/Advanced Molecular Imaging)

■ Firmware development for the PET Detector Tile, core part of the Philips PET/CT-Scanner

■ Fully responsible for the firmware development by PDPC, around the PET Detector Tile and associated infrastructure systems

■ FPGA, software and script programming (VHDL, C/C++, Lua, TCL, Python) in Windows & Ubuntu Linux

■ Automation of compilation processes with TCL scripts

■ Implementation of complex FPGA blocks/algorithms and delivery of various portable IP blocks

■ Programming of high-speed interfaces (processing and transmission of large amounts of data at high data rates)

■ Characterization and selection of hardware components

■ Automation of characterization of relevant parameters by plotting with Python

■ Refactoring and further development of existing Firmware

■ Version control and release management with Git and GitLab

■ Automation of V&V (Verification and Validation) with Lua and Python scripts

■ Provision of Firmware releases with corresponding documents: Requirements, Functional Descriptions, Test Specifications, Test Reports

■ Independent planning and execution of work packages (efforts, priorities) in consultation with the R&D Manager

■ Lab work and Handling of Radioactive Sources

■ Technical support for external customers

Altera (allg.), Digitaler Signalprozessor (DSP), Embedded Entwicklung / hardwarenahe Entwicklung, FPGA, Mentor Graphics, Quartus (Altera), Hardwarebeschreibungssprache, Vivado (Xilinx), FMEA (Failure Mode and Effects Analysis), Test Automation, C, C++, Eclipse, Git, Lua Scripting, Python, Tool Command Language, Projektmanagement, Technische Dokumentation