FPGA Ingenieur
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- 70565 Stuttgart
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- en | de
- 07.05.2024
Kurzvorstellung
Qualifikationen
Projekt‐ & Berufserfahrung
1/2016 – 1/2018
Tätigkeitsbeschreibung
Design of high speed data acquisition system from large pixel detector using 20xVirtex5 FPGA's having 32x10Gbps interfaces, including modeling, implementation, synthesis, verification and testing.
Organizing workshops and meetings for EUCALL (EU Horizon 2020 project) in collaboration with FEL’s of Europe and Laserlab Europe.
FPGA, Python
8/2015 – 12/2015
Tätigkeitsbeschreibung
See Front 3D solution: A system designed for single viewer, which enables to see three dimensional images without spectacles.
Real-time image acquisition from multiple HDMI based cameras and transmission to embedded computer over PCIE using Xilinx Artix 7 FPGA device.
Artix 7, PCIe, HDMI FPGA Developments.
FPGA
7/2012 – 4/2013
Tätigkeitsbeschreibung
Intel Data Plane Development Kit.
Software base high speed Packet processing.
C++, FPGA
4/2010 – 6/2012
Tätigkeitsbeschreibung
Accomplished wide array of tasks related to hardware design such as requirement gathering, translating those requirements into a digital hardware design, describing the required hardware using the HDL, creating test benches and running design simulations, synthesizing and implementing the design, finally testing the design on actual hardware.
Network Monitoring System
The data is collected from multiple 10Gbps links on CX4/fiber interface, then deep packet protocol analysis is performed. The project was acomplished by using Xilinx virtex5 FPGAs.
10Gbps Ethernet MAC
Implemented 10Gbps Ethernet MAC core utilizing XAUI core
PCIE and DMA
PCIE and DMA has been implemented for Xilinx Virtex-5 boards.
String Matching Core
The core was designed and developed to perform exact string matching on live network traffic at 5Gbps.
Webserver Implementation on Microblaze
Webserver was integrated with Network Monitoring System for configuring filters, inputs and outputs.
NVIDIA CUDA
Implementation of Aho-Corasik Algorithm for Exact String Matching for DPI at live 5Gbps traffic.
Embedded Linux
Link Aggregation and Load Balancing of Internet traffic using linux Distro.
URL Blocking System
Implemented URL Compression and Fast Searching for URL Blocking System
FPGA, C++
Ausbildung
Bremen
Persönliche Daten
- Englisch (Muttersprache)
- Deutsch (Fließend)
- Europäische Union
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