ASIC/FPGA Engineer

11/2022 – offen

FPGA design for Machine Vision Cameras
Design Verification
RTL Design
Device driver development

C++, Field Programmable Gate Array (FPGA), Python, VHDL (VHSIC Hardware Description Language)

5/2022 – 11/2022

RTL Design & (PCIe) IP integration
RTL Connectivity Verification using Jaspergold
CDC Verification

Field Programmable Gate Array (FPGA), TCL/TK, Verilog HDL, VHDL (VHSIC Hardware Description Language)

1/2021 – 5/2022

●Prototyping ASIC RTL design (Smart NIC) to FPGA (Xilinx, U280 card) .
● Writing IP wrappers, and interface adapters (native to industry standard AXI) for
IP integration.
● Synthesis, timing closure, and bitstream generation of complex designs.
● RTL simulation and debugging, including test development and writing test
benches.
● On-chip debugging using integrated logic analyzers.
● FPGA-based PCIe design (PCIe DMA, Dynamic Partial Reconfiguration of FPGA
through PCIe).

Field Programmable Gate Array (FPGA), Verilog HDL, Vivado (Xilinx)