Projekt‐ & Berufserfahrung
7/2013 – 1/2016Tätigkeitsbeschreibung
FPGA projects for military and civil aviation.
FPGA designer/developer, HW/SW integrations, FPGA verification, troubleshooting of the most complex issues
Embedded Entwicklung / hardwarenahe Entwicklung, Embedded Systems, MATLAB / Simulink
1/2012 – 4/2013Tätigkeitsbeschreibung
- Development of 2G (GSM), 3G (UMTS), 4G (LTE) DSP processing chains and Viterbi, physical layer 1 (PHY1) on FPGA.
- Strong focus on functional and performance improvements of digital signal processing with significant decrease of FPGA resources (FlipFlops-FFs, DSP48E, BRAMs, logic, FIR Compilers,...) and high timing improvements for reaching the final timing closure.
- Implementation of new DSP processing modules on FPGA devices.
- System Generator (SysGen), CoreGen, FPGA editor.
- Absolute control of SysGen: one of many examples is implementation of dedicated scripts for compilation and timing analysis of multiple runs similar to SmartExplorer in Xilinx ISE. BlackBox usage for solving special cases like different memory primitives of BRAMs.
- Debugging timing reports to achieve timing closure. Generation of clear and easy understandable suggestions for improvements both in SysGen and VHDL code.
- Application of manual timing constraints in SysGen based on properties of signal processing.
- Specific individual view on timing closure in FPGA, improvements and figures of merit.
- Complex Matlab simulations both in float and fixed point of wireless signals at different sampling rates.
- Implemented AGC functionality for 3G Rx, based on exp/log functions.
- Design of absolutely optimal multistage multi-rate filters, with multiple iterations in Matlab and CoreGen.
- Half band, CIC, FIR, IIR, multiplier less filters. Mix of innovative and well-known DSP solutions. Advanced filter design.
- Multichannel (hardware folding) and time multiplexing of FPGA resources.
- Mentor’s ModelSim simulations.
- Documentation provided on the implemented modules and on new tool development.
Embedded Entwicklung / hardwarenahe Entwicklung, MATLAB / Simulink, Embedded Software Engineering
Ort: Ljubljana, Slowenien
Ort: Belgrade, Serbien
Ort: Belgrade, Serbien
+ DO-254 FPGA design&development.
+ SDR (Software Defined Radio) in wireless 2G (GSM), 3G(UMTS), 4G(LTE) and for particle accelerators. Wireless Digital Signal Processing.
+ Matlab. Generation of algorithms using Matlab script, different toolboxes and Simulink.
+ Successfully developed different instruments for synchrotron light sources (particle accelerators), the world’s most advanced scientific and research facilities.
+ Expert on usage of Xilnx System Generator.
+ High speed and high-performance FPGA designs (300-400 MHz sampling frequency).
+ PCIe (FPGA) design.
+ Video processing (FPGA based): SD, HD, analog/digital input/output video streams.
+ Audio processing (FPGA&IC based).
+ Complex glue logic for many ICs (FPGA based as well).
+ General and proprietary military interfaces: MilBus-1553, Arinc-429, CAN, SPI, I2C, UART.
+ FPGA Verification experience.
+ Filtering: FIR, IIR, Half-Band, CIC, multiplierless structures, lattice, wavelet. Multi rate filters, polyphase.
+ AGC – Automatic Gain Control. Exp/log AGC function, and other implementations. Implemented in 3G Rx, accelerator instruments, V.34 modems.
+ Adaptive filtering: LMS (Least Mean Square), NLMS (Normalized LMS), RMS (Recursive Least Squares). System identification, noise and echo cancellation, complex equalizers.
+ Numerous modulators/demodulators: W-CDMA, OFDM, QAM, PSK (DPSK), DTMF, FSK, FM, PM, AM, Trellis-Coded (TCM).
+ Multi rate processing, multi stage multirate systems (decimation and interpolation including rational factors).
+ Digital Pre-Distortion – DPD for wireless systems.
+ FFT. Spectrum analysis.
+ Both time and frequency domain signal processing.
+ Texas Instruments DSP programming – Code Composer Studio (CCS). C54 and C64 DSPs.
+ Good knowledge of mobile infrastructure, WCDMA, UMTS.