Digital Design and Verification Engineer

I am a passionate ASIC Design/Verification engineer with 15 years of experience in digital design, possessing a large skill set and knowledge of design and verification. Excellent written and spoken communications skills and problem solving ability.

• Digital Design
• Digital Verification
• Firmware
• UVM
• Verilog HDL
• VHDL (VHSIC Hardware Description Language)

I am a Digital Design (ASIC)/Verification engineer with nine years experience in digital design, possessing a large skill set and knowledge of design and verification. I have excellent written and spoken communication skills and problem solving ability.

• Languages : VHDL, Verilog, System Verilog , 8051 Assembler, C/C embedded, TCL, Perl, UNIX
• Protocols : AMBA – AXI, APB, AHB; I2C, SPI, I2S, SWP
• Verification tools: Atrenta Spyglass, Cadence Comformal, OneSpin, Specman Elite
• Simulation tools: Mentor Modelsim, Cadence SimVision/NCSim
• Revision Control: Clearcase, SVN, DesignSync
• Operating systems: UNIX, SOLARIS, Red Hat Linux, Windows, MS DOS