Expert Hardware Designer

1/2014 – 1/2015

 Real-time & Online Speech Enhancement, 2014–2015
During this project time, I simulated almost all the speech enhancement methods using MATLAB. After quantitative analysis & comparison, C code for embedded ARM-based processors was generated in MATLAB. After complex modifications I ported the practical speech enhancement algorithms to an FPGA-based platform using AMD (Xilinx) Zynq SoC FPGAs. By accurate performance profiling, I selected a software-hardware co-design approach using ARM+FPGA platform for real-time high performance DSP algorithms for noise removal and speech enhancement. A GUI was designed using NI LabView to talk to the FPGA platform and select filter type, start, and stop filtering. In this project we did not assume any specific noise distribution and type, thus complex DSP algorithms needed to be implemented for automatic noise type identification and removal. More specifically the following algorithms were implemented using an SoC FPGA-based software/hardware co-design approach:
• Adaptive Filtering
• Statistical-based Methods
• Kalman Filtering
• Space Subtraction
• Subspace Algorithms
• Wiener Filtering
• Wavelet Denoising

Computer Engineering, Digitaler Signalprozessor (DSP), Embedded Linux, Spracherkennung, Echtzeit-Softwareentwickler, Filtertechnik, FPGA

1/2013 – 1/2015

 FPGA-based Custom SoPC, 2013-2015
We designed an SoPC (System on Programmable Chip) for DSP applications with emphasis on image processing. The SoC consisted a domestic implementation of SPARC processor architecture with floating point arithmetic support, and extensive peripherals and interfaces around it. The SoC was implemented on an Intel (ALTERA) FPGA and a custom PCB was designed and fabricated for the project. The SoC consisted of the following FPGA-based IP cores:
• SPARC Processor
• AMBA AHB Bus
• AMBA APB Bus
• DMA
• Vector Interrupt Controller
• Instruction & Data Memories
• 4 UART, 4 SPI, 3 Timer/Counter, GPIO
• Watchdog Timer
• Flash Memory
• External Memory Interface
• Boot, Clock, Reset, and Debug Modules

Computer Engineering, Digitaler Signalprozessor (DSP), Embedded Systems, Hardware-Design, Hardwarebeschreibungssprache, Microchipentwickler, FPGA

1/2012 – 1/2014

 Layer 2 Managed Switch, 2012-2014
During this project interval I was the leader and manager of a team, designing an FPGA-based network layer 2 switch. The switch had eight 10/100/1000 Ethernet ports and two 10G uplink ports. A customized Linux OS running on an ARM processor was in charge of management layer and control software. The FPGA architecture designed to be high performance, with any-to-any switching capability, with an aggregate bandwidth of 2×8×1Gbps. The following IP cores were designed and implemented on a custom PCB, featuring an AMD (Xilinx) FPGA:
• 10G Ethernet MAC
• 10G GTX Transceivers
• Tri-mode Gigabit Ethernet MAC
• 8×8 Nonblocking Crossbar Switch
• Content Addressable Memory
• External memory Interface
• VLAN Tagging in Compliance with IEEE 802.1Q
• High Performance MAC Address & IP Lookup Engine
• Address Monitor & Aging IP Core
• Custom Hardware Encryption Engine

IT Ingenieur-Infrastruktur, Embedded Linux, Embedded Systems, Hardware-Design, Hardwarebeschreibungssprache, Network Architect, Infrastrukturarchitektur, Vermittlungstechnik, FPGA

1/2011 – 1/2013

 ASIC SoC for WSN Applications, 2011-2013
We designed an SoC for DSP applications with emphasis on Wireless Sensor Networks (WSN). The SoC had an ultra-low power consumption and included a CPU architecture with custom instructions for WSN applications. It also featured a DSP engine accelerator, program and data memory, clocking and several boot modes plus necessary peripherals. The prototype was tested on Xilinx FPGAs. The ASIC implementation on 180 nm TSMC fabrication process successfully passed tests.

FPGA, Hardware-Design, Microchipentwickler, Hochfrequenztechnik