B2B Semiconductors Project Manager

7/2006 – 8/2015

Architected high-security Chip-card SLE78 and SLE90 microcontrollers family.
Digital design of multi-clock interface management and digital power control subsystems.
Milestone delivery planning and enabling.
Chip top-level integration, change- and configuration-management.
Design sign-off coordination.
Product security certification (Common Criteria) support.

Hardware Entwicklung, ModelSim (Mentor Graphics), Verilog HDL, VHDL (VHSIC Hardware Description Language), System Analyse, System Architektur, System Design, Teamentwicklung, Mikrocontroller

5/2003 – 6/2006

Development of architecture and concept of ultrafast video capturing systems.
FPGA design team leadership.
System architecture design.
EDA tools park supervision and development.
Communication and customers requirements capture.

Field Programmable Gate Array (FPGA), Hardware Entwicklung, ModelSim (Mentor Graphics), VHDL (VHSIC Hardware Description Language), Projektleitung / Teamleitung (IT), System Analyse, System Architektur, System Design, Teamentwicklung

9/2000 – 4/2003

Deployed bus functional models for OIF SPI-4.2, Utopia Level 3, CSIX interfaces for Q192 ASIC.
Maintained functional regression at module and system levels.
Architected Synopsys VERA-HVL verification environment and behavioral models.
Designed RTL sub-hierarchy and proprietary high-speed ASIC bus interface.
Authored technical documentation of Q192 and OC48 ASIC projects.

ModelSim (Mentor Graphics), Verilog HDL, VHDL (VHSIC Hardware Description Language), Systems Simulation, CAD (computer-aided design)

9/1997 – 8/2000

Developed and delivered course lectures and labs on digital design, ASIC testing, FPGA design and verification.
Supervised R&D projects and co-operation activities under EUROCHIP/EUROPRACTICE frame-
work

Altera (allg.), Hardware Entwicklung, ModelSim (Mentor Graphics), VHDL (VHSIC Hardware Description Language), Xilinx (allg.), Automatisierungstechnik (allg.), CAD (computer-aided design)