Archiviertes Projekt - FPGA Engineer

Work exp:3+ years

Project Duration: 9 months & extendable



Location: Heidelberg

Work Authorization : EU Citizens

Working model : 100% ONSITE No Remote allowed

Language: English

Job Role:

FPGA development:
- perform design document updates (DDD)
- implementation FPGA (Xilinx Zync, Vivado, AXI stream, memory controller interface)
- define and prepare test setup, test execution

HW design and development:
- Digital HW Design
- Cable design
- Update documentation (test procedure and test report, ICD update, ATP documentation)
- prepare HW for tests, prepare and execute integration tests
- Failure investigation


Mandatory Skills:

VHDL Verification
Tools: Xilinx Zync,/Vivado