Digital Design Engineer (FPGA, ASIC, 100% Remote)

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  • März 2021
  • September 2021
  • D-80331 München
  • auf Anfrage
  • Remote
  • 23.02.2021

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Projektbeschreibung

We've partnered with a technical development firm who are searching for an experienced digital ASIC/FPGA engineer. Main activity will be RTL implementation (either in Verilog or VHDL) and verification (in System-Verilog) of components for a Digital Baseband for a radio system.

The specification of the to-be-implemented components is usually in Matlab / Python.

Requirements:
- 5+ years experience with Verilog (or VHDL) experience for RTL implementation, both for FPGA and ASIC
- SystemVerilog experience for testbench development
- Good understanding of Matlab / Python and able to use it for integration in the testbenches (to make it self-checking).
- Able to document the implemented components.

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